Performing non-maximum suppression in parallel

ABSTRACT

Apparatuses, systems, and techniques to perform non-maximum suppression (NMS) in parallel to remove redundant bounding boxes. In at least one embodiment, two or more parallel circuits to perform two or more portions of a NMS algorithm in parallel to remove one or more redundant bounding boxes corresponding to one or more objects within one or more digital images.

TECHNICAL FIELD

At least one embodiment pertains to processing resources used to performand facilitate artificial intelligence. For example, at least oneembodiment pertains to processors or computing systems used to train anduse neural networks according to various novel techniques describedherein.

BACKGROUND

Neural networks can be used for object detection tasks. A neural networkcan perform an object detection task that identifies one or morebounding boxes in which an object is detected and provides a confidencescore for each bounding box. An object detection task can identifymultiple overlapping candidate windows around an object with similarscores. A suppression algorithm can be used to remove redundant boundingboxes.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A illustrates inference and/or training logic, according to atleast one embodiment;

FIG. 1B illustrates inference and/or training logic, according to atleast one embodiment;

FIG. 2 illustrates training and deployment of a neural network,according to at least one embodiment;

FIG. 3 is an example data flow diagram for a process to perform parallelnon-maximum suppression (NMS), according to at least one embodiment;

FIG. 4 is an example data flow diagram for a process in which multiplesuppression processes are performed in parallel, according to at leastone embodiment;

FIG. 5 illustrates a visual representation of a neural network withmultiple layers for object detection and a layer for parallel NMS,according to at least one embodiment;

FIG. 6 illustrates a bounding box suppression process, according to atleast one embodiment;

FIG. 7 illustrates a reduced search space for parallel NMS, according toat least one embodiment;

FIG. 8 is a flow diagram of a method of performing two or more portionsof a NMS algorithm in parallel to remove one or more redundant boundingboxes, according to at least one embodiment;

FIG. 9 illustrates an example data center system, according to at leastone embodiment;

FIG. 10A illustrates an example of an autonomous vehicle, according toat least one embodiment;

FIG. 10B illustrates an example of camera locations and fields of viewfor an autonomous vehicle of FIG. 10A, according to at least oneembodiment;

FIG. 10C is a block diagram illustrating an example system architecturefor an autonomous vehicle of FIG. 10A, according to at least oneembodiment;

FIG. 10D is a diagram illustrating a system for communication betweencloud-based server(s) and an autonomous vehicle of FIG. 10A, accordingto at least one embodiment;

FIG. 11 is a block diagram illustrating a computer system, according toat least one embodiment;

FIG. 12 is a block diagram illustrating a computer system, according toat least one embodiment;

FIG. 13 illustrates a computer system, according to at least oneembodiment;

FIG. 14 illustrates a computer system, according to at least oneembodiment;

FIG. 15A illustrates a computer system, according to at least oneembodiment;

FIG. 15B illustrates a computer system, according to at least oneembodiment;

FIG. 15C illustrates a computer system, according to at least oneembodiment;

FIG. 15D illustrates a computer system, according to at least oneembodiment;

FIGS. 15E and 15F illustrate a shared programming model, according to atleast one embodiment;

FIG. 16 illustrates exemplary integrated circuits and associatedgraphics processors, according to at least one embodiment;

FIGS. 17A-17B illustrate exemplary integrated circuits and associatedgraphics processors, according to at least one embodiment;

FIGS. 18A-18B illustrate additional exemplary graphics processor logicaccording to at least one embodiment;

FIG. 19 illustrates a computer system, according to at least oneembodiment;

FIG. 20A illustrates a parallel processor, according to at least oneembodiment;

FIG. 20B illustrates a partition unit, according to at least oneembodiment;

FIG. 20C illustrates a processing cluster, according to at least oneembodiment;

FIG. 20D illustrates a graphics multiprocessor, according to at leastone embodiment;

FIG. 21 illustrates a multi-graphics processing unit (GPU) system,according to at least one embodiment;

FIG. 22 illustrates a graphics processor, according to at least oneembodiment;

FIG. 23 is a block diagram illustrating a processor micro-architecturefor a processor, according to at least one embodiment;

FIG. 24 illustrates a deep learning application processor, according toat least one embodiment;

FIG. 25 is a block diagram illustrating an example neuromorphicprocessor, according to at least one embodiment;

FIG. 26 illustrates at least portions of a graphics processor, accordingto one or more embodiments;

FIG. 27 illustrates at least portions of a graphics processor, accordingto one or more embodiments;

FIG. 28 illustrates at least portions of a graphics processor, accordingto one or more embodiments;

FIG. 29 is a block diagram of a graphics processing engine of a graphicsprocessor in accordance with at least one embodiment;

FIG. 30 is a block diagram of at least portions of a graphics processorcore, according to at least one embodiment;

FIGS. 31A-31B illustrate thread execution logic including an array ofprocessing elements of a graphics processor core according to at leastone embodiment;

FIG. 32 illustrates a parallel processing unit (“PPU”), according to atleast one embodiment;

FIG. 33 illustrates a general processing cluster (“GPC”), according toat least one embodiment;

FIG. 34 illustrates a memory partition unit of a parallel processingunit (“PPU”), according to at least one embodiment;

FIG. 35 illustrates a streaming multi-processor, according to at leastone embodiment.

FIG. 36 is an example data flow diagram for an advanced computingpipeline, in accordance with at least one embodiment;

FIG. 37 is a system diagram for an example system for training,adapting, instantiating and deploying machine learning models in anadvanced computing pipeline, in accordance with at least one embodiment;

DETAILED DESCRIPTION Inference and Training Logic

FIG. 1A illustrates inference and/or training logic 115 used to performinferencing and/or training operations associated with one or moreembodiments. Details regarding inference and/or training logic 115 areprovided below in conjunction with FIGS. 1A and/or 1B.

In at least one embodiment, inference and/or training logic 115 mayinclude, without limitation, code and/or data storage 101 to storeforward and/or output weight and/or input/output data, and/or otherparameters to configure neurons or layers of a neural network trainedand/or used for inferencing in aspects of one or more embodiments. In atleast one embodiment, training logic 115 may include, or be coupled tocode and/or data storage 101 to store graph code or other software tocontrol timing and/or order, in which weight and/or other parameterinformation is to be loaded to configure, logic, including integerand/or floating point units (collectively, arithmetic logic units (ALUs)or simply circuits). In at least one embodiment, code, such as graphcode, loads weight or other parameter information into processor ALUsbased on an architecture of a neural network to which such codecorresponds. In at least one embodiment, code and/or data storage 101stores weight parameters and/or input/output data of each layer of aneural network trained or used in conjunction with one or moreembodiments during forward propagation of input/output data and/orweight parameters during training and/or inferencing using aspects ofone or more embodiments. In at least one embodiment, any portion of codeand/or data storage 101 may be included with other on-chip or off-chipdata storage, including a processor's L1, L2, or L3 cache or systemmemory.

In at least one embodiment, any portion of code and/or data storage 101may be internal or external to one or more processors or other hardwarelogic devices or circuits. In at least one embodiment, code and/or codeand/or data storage 101 may be cache memory, dynamic randomlyaddressable memory (“DRAM”), static randomly addressable memory(“SRAM”), non-volatile memory (e.g., flash memory), or other storage. Inat least one embodiment, a choice of whether code and/or code and/ordata storage 101 is internal or external to a processor, for example, orcomprising DRAM, SRAM, flash or some other storage type may depend onavailable storage on-chip versus off-chip, latency requirements oftraining and/or inferencing functions being performed, batch size ofdata used in inferencing and/or training of a neural network, or somecombination of these factors.

In at least one embodiment, inference and/or training logic 115 mayinclude, without limitation, a code and/or data storage 105 to storebackward and/or output weight and/or input/output data corresponding toneurons or layers of a neural network trained and/or used forinferencing in aspects of one or more embodiments. In at least oneembodiment, code and/or data storage 105 stores weight parameters and/orinput/output data of each layer of a neural network trained or used inconjunction with one or more embodiments during backward propagation ofinput/output data and/or weight parameters during training and/orinferencing using aspects of one or more embodiments. In at least oneembodiment, training logic 115 may include, or be coupled to code and/ordata storage 105 to store graph code or other software to control timingand/or order, in which weight and/or other parameter information is tobe loaded to configure, logic, including integer and/or floating pointunits (collectively, arithmetic logic units (ALUs).

In at least one embodiment, code, such as graph code, causes loading ofweight or other parameter information into processor ALUs based on anarchitecture of a neural network to which such code corresponds. In atleast one embodiment, any portion of code and/or data storage 105 may beincluded with other on-chip or off-chip data storage, including aprocessor's L1, L2, or L3 cache or system memory. In at least oneembodiment, any portion of code and/or data storage 105 may be internalor external to one or more processors or other hardware logic devices orcircuits. In at least one embodiment, code and/or data storage 105 maybe cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory),or other storage. In at least one embodiment, a choice of whether codeand/or data storage 105 is internal or external to a processor, forexample, or comprising DRAM, SRAM, flash memory or some other storagetype may depend on available storage on-chip versus off-chip, latencyrequirements of training and/or inferencing functions being performed,batch size of data used in inferencing and/or training of a neuralnetwork, or some combination of these factors.

In at least one embodiment, code and/or data storage 101 and code and/ordata storage 105 may be separate storage structures. In at least oneembodiment, code and/or data storage 101 and code and/or data storage105 may be a combined storage structure. In at least one embodiment,code and/or data storage 101 and code and/or data storage 105 may bepartially combined and partially separate. In at least one embodiment,any portion of code and/or data storage 101 and code and/or data storage105 may be included with other on-chip or off-chip data storage,including a processor's L1, L2, or L3 cache or system memory.

In at least one embodiment, inference and/or training logic 115 mayinclude, without limitation, one or more arithmetic logic unit(s)(“ALU(s)”) 110, including integer and/or floating point units, toperform logical and/or mathematical operations based, at least in parton, or indicated by, training and/or inference code (e.g., graph code),a result of which may produce activations (e.g., output values fromlayers or neurons within a neural network) stored in an activationstorage 120 that are functions of input/output and/or weight parameterdata stored in code and/or data storage 101 and/or code and/or datastorage 105. In at least one embodiment, activations stored inactivation storage 120 are generated according to linear algebraic andor matrix-based mathematics performed by ALU(s) 110 in response toperforming instructions or other code, wherein weight values stored incode and/or data storage 105 and/or data storage 101 are used asoperands along with other values, such as bias values, gradientinformation, momentum values, or other parameters or hyperparameters,any or all of which may be stored in code and/or data storage 105 orcode and/or data storage 101 or another storage on or off-chip.

In at least one embodiment, ALU(s) 110 are included within one or moreprocessors or other hardware logic devices or circuits, whereas in atleast one other embodiment, ALU(s) 110 may be external to a processor orother hardware logic device or circuit that uses them (e.g., aco-processor). In at least one embodiment, ALUs 110 may be includedwithin a processor's execution units or otherwise within a bank of ALUsaccessible by a processor's execution units either within same processoror distributed between different processors of different types (e.g.,central processing units, graphics processing units, fixed functionunits, etc.). In at least one embodiment, code and/or data storage 101,code and/or data storage 105, and activation storage 120 may share aprocessor or other hardware logic device or circuit, whereas in at leastone other embodiment, they may be in different processors or otherhardware logic devices or circuits, or some combination of same anddifferent processors or other hardware logic devices or circuits. In atleast one embodiment, any portion of activation storage 120 may beincluded with other on-chip or off-chip data storage, including aprocessor's L1, L2, or L3 cache or system memory. Furthermore,inferencing and/or training code may be stored with other codeaccessible to a processor or other hardware logic or circuit and fetchedand/or processed using a processor's fetch, decode, scheduling,execution, retirement and/or other logical circuits.

In at least one embodiment, activation storage 120 may be cache memory,DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage.In at least one embodiment, activation storage 120 may be completely orpartially within or external to one or more processors or other logicalcircuits. In at least one embodiment, a choice of whether activationstorage 120 is internal or external to a processor, for example, orcomprising DRAM, SRAM, flash memory or some other storage type maydepend on available storage on-chip versus off-chip, latencyrequirements of training and/or inferencing functions being performed,batch size of data used in inferencing and/or training of a neuralnetwork, or some combination of these factors.

In at least one embodiment, inference and/or training logic 115illustrated in FIG. 1A may be used in conjunction with anapplication-specific integrated circuit (“ASIC”), such as a TensorFlow®Processing Unit from Google, an inference processing unit (IPU) fromGraphcore™, or a Nervana® (e.g., “Lake Crest”) processor from IntelCorp. In at least one embodiment, inference and/or training logic 115illustrated in FIG. 1A may be used in conjunction with centralprocessing unit (“CPU”) hardware, graphics processing unit (“GPU”)hardware or other hardware, such as field programmable gate arrays(“FPGAs”).

FIG. 1B illustrates inference and/or training logic 115, according to atleast one embodiment. In at least one embodiment, inference and/ortraining logic 115 may include, without limitation, hardware logic inwhich computational resources are dedicated or otherwise exclusivelyused in conjunction with weight values or other informationcorresponding to one or more layers of neurons within a neural network.In at least one embodiment, inference and/or training logic 115illustrated in FIG. 1B may be used in conjunction with anapplication-specific integrated circuit (ASIC), such as TensorFlow®Processing Unit from Google, an inference processing unit (IPU) fromGraphcore™, or a Nervana® (e.g., “Lake Crest”) processor from IntelCorp. In at least one embodiment, inference and/or training logic 115illustrated in FIG. 1B may be used in conjunction with centralprocessing unit (CPU) hardware, graphics processing unit (GPU) hardwareor other hardware, such as field programmable gate arrays (FPGAs). In atleast one embodiment, inference and/or training logic 115 includes,without limitation, code and/or data storage 101 and code and/or datastorage 105, which may be used to store code (e.g., graph code), weightvalues and/or other information, including bias values, gradientinformation, momentum values, and/or other parameter or hyperparameterinformation. In at least one embodiment illustrated in FIG. 1B, each ofcode and/or data storage 101 and code and/or data storage 105 isassociated with a dedicated computational resource, such ascomputational hardware 102 and computational hardware 106, respectively.In at least one embodiment, each of computational hardware 102 andcomputational hardware 106 comprises one or more ALUs that performmathematical functions, such as linear algebraic functions, only oninformation stored in code and/or data storage 101 and code and/or datastorage 105, respectively, result of which is stored in activationstorage 120.

In at least one embodiment, each of code and/or data storage 101 and 105and corresponding computational hardware 102 and 106, respectively,correspond to different layers of a neural network, such that resultingactivation from one storage/computational pair 101/102 of code and/ordata storage 101 and computational hardware 102 is provided as an inputto a next storage/computational pair 105/106 of code and/or data storage105 and computational hardware 106, in order to mirror a conceptualorganization of a neural network. In at least one embodiment, each ofstorage/computational pairs 101/102 and 105/106 may correspond to morethan one neural network layer. In at least one embodiment, additionalstorage/computation pairs (not shown) subsequent to or in parallel withstorage/computation pairs 101/102 and 105/106 may be included ininference and/or training logic 115.

Neural Network Training and Deployment

FIG. 2 illustrates training and deployment of a deep neural network,according to at least one embodiment. In at least one embodiment,untrained neural network 206 is trained using a training dataset 202. Inat least one embodiment, training framework 204 is a PyTorch framework,whereas in other embodiments, training framework 204 is a TensorFlow,Boost, Caffe, Microsoft Cognitive Toolkit/CNTK, MXNet, Chainer, Keras,Deeplearning4j, or other training framework. In at least one embodiment,training framework 204 trains an untrained neural network 206 andenables it to be trained using processing resources described herein togenerate a trained neural network 208. In at least one embodiment,weights may be chosen randomly or by pre-training using a deep beliefnetwork. In at least one embodiment, training may be performed in eithera supervised, partially supervised, or unsupervised manner.

In at least one embodiment, untrained neural network 206 is trainedusing supervised learning, wherein training dataset 202 includes aninput paired with a desired output for an input, or where trainingdataset 202 includes input having a known output and an output of neuralnetwork 206 is manually graded. In at least one embodiment, untrainedneural network 206 is trained in a supervised manner and processesinputs from training dataset 202 and compares resulting outputs againsta set of expected or desired outputs. In at least one embodiment, errorsare then propagated back through untrained neural network 206. In atleast one embodiment, training framework 204 adjusts weights thatcontrol untrained neural network 206. In at least one embodiment,training framework 204 includes tools to monitor how well untrainedneural network 206 is converging towards a model, such as trained neuralnetwork 208, suitable to generating correct answers, such as in result214, based on input data such as a new dataset 212. In at least oneembodiment, training framework 204 trains untrained neural network 206repeatedly while adjust weights to refine an output of untrained neuralnetwork 206 using a loss function and adjustment algorithm, such asstochastic gradient descent. In at least one embodiment, trainingframework 204 trains untrained neural network 206 until untrained neuralnetwork 206 achieves a desired accuracy. In at least one embodiment,trained neural network 208 can then be deployed to implement any numberof machine learning operations.

In at least one embodiment, untrained neural network 206 is trainedusing unsupervised learning, wherein untrained neural network 206attempts to train itself using unlabeled data. In at least oneembodiment, unsupervised learning training dataset 202 will includeinput data without any associated output data or “ground truth” data. Inat least one embodiment, untrained neural network 206 can learngroupings within training dataset 202 and can determine how individualinputs are related to untrained dataset 202. In at least one embodiment,unsupervised training can be used to generate a self-organizing map intrained neural network 208 capable of performing operations useful inreducing dimensionality of new dataset 212. In at least one embodiment,unsupervised training can also be used to perform anomaly detection,which allows identification of data points in new dataset 212 thatdeviate from normal patterns of new dataset 212.

In at least one embodiment, semi-supervised learning may be used, whichis a technique in which in training dataset 202 includes a mix oflabeled and unlabeled data. In at least one embodiment, trainingframework 204 may be used to perform incremental learning, such asthrough transferred learning techniques. In at least one embodiment,incremental learning enables trained neural network 208 to adapt to newdataset 212 without forgetting knowledge instilled within trained neuralnetwork 208 during initial training.

Parallel NMS

Embodiments described below are directed to parallelization ofnon-maximum suppression (NMS) of bounding boxes (and/or other boundingshapes such as circles, ellipses, etc.) in connection with an objectdetection task. NMS is an algorithm that removes redundant boundingboxes (and/or other bounding shapes) for an object detection task, suchas performed by an object detection pipeline. Existing NMS algorithmsmay sort a list of bounding boxes (and/or other bounding shapes) in adescending order of confidence values and compute an intersection overunion (IoU) value between all candidate boxes. Some NMS algorithms mayperform IoU computations in parallel, but because they rely on sortingbounding boxes (and/or other bounding shapes) and handling boundingboxes (and/or other bounding shapes) in a descending order, these NMSalgorithms cannot fully parallelize suppression of bounding boxes(and/or other bounding shapes). In at least one embodiment, anydiscussion of bounding boxes herein also applies to other types ofbounding shapes.

In at least one embodiment, suppression of bounding boxes isparallelized by performing two or more portions of an NMS algorithm inparallel to remove one or more redundant bounding boxes corresponding toone or more objects within one or more digital images. In at least oneembodiment, removing or suppressing redundant bounding boxescorresponding to one or more objects involves initiating multiplesuppression processes of an NMS algorithm and constraining eachsuppression process to an area surrounding a candidate point of arespective bounding box. In at least one embodiment, this area, alsoreferred to as a search space, defines a subset of candidate boundingboxes to be evaluated for each suppression process. In at least oneembodiment, for a respective bounding box, a separate suppressionprocess can be performed to determine whether a respective bounding boxshould be suppressed based on comparisons with only neighboring boundingboxes within an area around a candidate point associated with arespective bounding box. In at least one embodiment, comparisons includeconfidence value comparisons and IoU comparisons. In at least oneembodiment, separate suppression processes are performed in parallel,thereby fully parallelizing performance of an NMS algorithm. In at leastone embodiment, a point in a confidence feature map corresponds to acandidate bounding box. In at least one embodiment, a point in aconfidence feature map corresponds to multiple candidate bounding boxes.In at least one embodiment, a neighboring point can be determined byapplying one or more distance metrics on a feature map space.

FIG. 3 is an example data flow diagram for a method 300 to performparallel NMS, according to at least one embodiment. In at least oneembodiment, method 300 is performed by interference and/or traininglogic 115. Details regarding inference and/or training logic 115 areprovided herein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used in systemFIG. 10B for inferencing or predicting operations based, at least inpart, on weight parameters calculated using neural network trainingoperations, neural network functions and/or architectures, or neuralnetwork use cases described herein.

Referring to FIG. 3, in at least one embodiment, processing logicobtains (e.g., retrieves from a data store) one or more digital images(block 302). In at least one embodiment, processing logic performs anobject detection task to detect one or more objects within one or moredigital images (block 302). In at least one embodiment, at block 302,processing logic uses a CNN detector in which it slides a window aroundan image and extracts features (e.g., edges, corners, blobs, ridges,edge direction, borders, shapes, etc.) for classification. In at leastone embodiment, at block 302, processing logic uses an end-to-enddetector to extract features directly from input images. In at least oneembodiment at block 302, processing logic classifies features extractedin a window and accepts a window as a candidate bounding box if a scoreof extracted features is above a threshold (also referred to as apositive candidate bounding box). In at least one embodiment,classification of features can determine whether an object is containedwithin a window. In at least one embodiment, in a detection phase, animage can be scanned at one or more windows of varying sizes andlocations and features can be extracted from one or more windows ofvarying sizes. In at least one embodiment, a classifier can be run onall scales of an image (image sizes) and can determine confidencescores, indicative of whether a window containing an object.

In at least one embodiment, one or more feature maps with multiplebounding boxes can be obtained from an output of a trained machinelearning model such as an artificial neural network. One exampleartificial neural network that may be used to generate bounding boxes isa convolutional neural network (CNN). In at least one embodiment, one ormore CNNs are trained to receive images as input and to output boundingboxes around one or more regions and/or objects from said input images.In at least one embodiment, one or more CNNs are trained to performobject detection and/or object recognition for one or more types ofobjects, for example, and to generate one or multiple bounding boxesaround detected and/or recognized objects. In at least one embodiment, aCNN outputs multiple bounding boxes that are associated with a sameobject, region or feature in an image. In at least one embodiment, eachoutput bounding box may be associated with or include a confidence valueand/or a probability value. In at least one embodiment, one or morefeature maps with multiple bounding boxes are obtained from a forwardinference layer of a neural network (e.g., a CNN). In at least oneembodiment, one or more digital images are received by a trained neuralnetwork that outputs an output feature map with multiple bounding boxes.

In at least one embodiment at block 302, processing logic outputs one ormore output feature maps with multiple bounding boxes and correspondingconfidence scores, where an output feature map can include multiplepoints each corresponding to a bounding box and having a confidencescore. In at least one embodiment, at block 302, processing logicoutputs an output feature map with multiple redundant bounding boxes(block 306). In at least one embodiment, for output confidence featuremap F(M,N) where each point p∈F(M, N), a delete mask delete_mask isused, where delete_mask=D(M,N). In at least one embodiment, each flag indelete_mask indicates whether a certain box should be deleted.

In at least one embodiment, instead of performing NMS consecutively bycomparing each point included in an output feature map to all otherpoints, processing logic performs parallel NMS by comparing a candidatepoint with only a subset of neighboring points from an output featuremap to remove one or more redundant bounding boxes corresponding to oneor more objects within one or more digital images (block 308). In atleast one embodiment, at block 308, processing logic constrains eachparallel suppression process to an area (also referred to as searchspace) surrounding a candidate point corresponding to a candidatebounding box and its corresponding neighboring points corresponding toneighboring bounding boxes, thereby defining a subset of multiplebounding boxes for each suppression process. In at least one embodiment,processing logic outputs one or more output feature maps with one ormore redundant bounding boxes removed (block 310).

In at least one embodiment, at block 308, processing logic identifies aset of candidate points from an output feature map comprising aplurality of points, each point in an output feature map correspondingto a bounding box and comprising a confidence score. In at least oneembodiment, each point of a set of candidate points includes aconfidence score that satisfies (e.g., is greater than) a confidencethreshold. In at least one embodiment, processing logic initiates one ofa plurality of parallel suppression processes with respect to eachcandidate point, such as illustrated in FIG. 4. In at least oneembodiment, for each candidate point in a parallel suppression process,processing logic identifies a set of neighboring points that are withinan area surrounding a respective candidate point (e.g., within aparticular distance from a candidate point).

In at least one embodiment, processing logic is performed by a layer ofa neural network. In at least one embodiment, a neural network includesmultiple layers and an output layer. In at least one embodiment,multiple layers of a neural network obtain an output feature map withmultiple redundant bounding boxes corresponding to one or more objectswithin one or more digital images at block 306 and an output layerperforms parallel NMS to remove one or more redundant bounding boxes atblock 308. In at least one embodiment, an output layer identifies a setof bounding boxes corresponding to one or more objects within one ormore digital images at block 306 and performs parallel NMS to remove oneor more redundant bounding boxes at block 308.

FIG. 4 is an example data flow diagram for a method 400 in whichmultiple suppression sub-processes are performed in parallel by parallelcircuits, according to at least one embodiment. In at least oneembodiment, method 400 is performed by interference and/or traininglogic 115. Details regarding inference and/or training logic 115 areprovided herein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used in systemFIG. 10B for inferencing or predicting operations based, at least inpart, on weight parameters calculated using neural network trainingoperations, neural network functions and/or architectures, or neuralnetwork use cases described herein.

Referring to FIG. 4, in at least one embodiment, a first circuit 402receives an output feature map 401 with multiple redundant boundingboxes. In at least one embodiment, output feature map 401 includesmultiple points and each point corresponds to a bounding box and has aconfidence score. In at least one embodiment, a point can be a centerpoint of a bounding box. In at least one embodiment, a point can beanother point of a bounding box, such as a point at a corner or an edgeof a bounding box. In at least one embodiment, first circuit 402identifies a set of candidate points from output feature map 401. In atleast one embodiment, a candidate point is a point having a confidencescore that satisfies (e.g., is greater than) a confidence threshold. Inat least one embodiment, a confidence threshold is programmable (e.g.,0.1). In at least one embodiment, first circuit 402 initiates a separatesuppression sub-process of multiple parallel suppression sub-processesto be performed by parallel circuits 404-410 for each candidate point.In at least one embodiment, a number of M×N sub-processes can beperformed. In at least one embodiment, first circuit 402 identifies, foreach candidate point, a set of neighboring points that are within anarea of a respective candidate point before or after initiating arespective suppression sub-process of parallel suppression sub-processesto be performed by parallel circuits 404-410. In at least oneembodiment, each suppression sub-process can first determine whether atarget point in an output feature map should be processed by determiningwhether a confidence value satisfies (e.g., is less than) a threshold(e.g., conf<0.1). In at least one embodiment, if a confidence value of atarget point satisfies (e.g., is less than) a threshold, a target pointcan be removed from consideration without further processing. In atleast one embodiment, two thresholds can be used at two different pointsduring processing such as a first threshold can be used initially todetermine whether a point in an output feature map is a candidate pointand a second threshold is used subsequently in a IOU comparison todetermine whether a candidate point that satisfied a first thresholdcorresponds to a redundant bounding box. In at least one embodiment,points in an output feature map that are greater than a first thresholdcan be processed as candidate points by parallel suppressionsub-processes that use a second threshold, which is greater than a firstthreshold, to determine whether a candidate point that satisfied a firstthreshold corresponds to a redundant bounding box.

In at least one embodiment, each of parallel suppression sub-processes,performed by parallel circuits 404-410, identifies a set of neighboringpoints that are within an area of a respective candidate point onceinitiated. For example, in at least one embodiment, first parallelsuppression sub-process, performed by second circuit 404, identifies afirst set of neighboring points that are within an area of a firstcandidate point and a parallel suppression sub-process, performed bythird circuit 406, identifies a second set of neighboring points thatare within an area of a second candidate point. Similarly, in at leastone embodiment, parallel suppression sub-processes, performed by thirdcircuit 408 and Nth circuit 410, each identify a respective set ofneighboring points that are within an area of a respective candidatepoint.

In at least one embodiment, first circuit 402 or parallel circuits404-410 identify a set of neighboring points by calculating a distancebetween a candidate point and another point in an output feature map andidentifying it as a neighboring point responsive to a distance beingless than a distance threshold. In at least one embodiment, a distancethreshold defines an area (a search space) that surrounds a respectivecandidate point and includes a set of neighboring points.

In at least one embodiment, each parallel suppression sub-processes,performed by parallel circuits 404-410, calculates an IoU value of acandidate point and a neighboring point within a search space anddetermines whether an IoU value satisfies (e.g., is greater than) a IoUthreshold and a confidence score of a candidate point satisfies acriterion pertaining to a confidence score of a neighboring point (e.g.,a confidence score of a candidate point is less than a confidence scoreof a neighboring point). In at least one embodiment, each parallelsuppression sub-processes, performed by parallel circuits 404-410,identifies a candidate point as corresponding to a redundant boundingbox to be removed responsive to an IoU value satisfying (e.g., beinggreater than) an IoU threshold and a confidence score of a positivecandidate point satisfying a criterion pertaining to (e.g., being lessthan) a confidence score of a neighboring point. This can be repeatedfor each neighboring point in a set of neighboring points that arewithin an area or search space associated with a candidate point. In atleast one embodiment, a set of neighboring points can be zero or morecandidate points that are within an area surrounding a respectivecandidate point. For example, in at least one embodiment, first parallelsuppression sub-process, which is initiated with respect to a firstcandidate point and performed by second circuit 404, calculates an IoUvalue of first candidate point and a neighboring point. In at least oneembodiment, first parallel suppression sub-process, which is performedby second circuit 404, determines whether an IoU value satisfies (e.g.,is greater than) an IoU threshold and whether a confidence score of acandidate point satisfies a criterion pertaining to (e.g., is less than)a confidence score of a neighboring point. In at least one embodiment,first parallel suppression sub-process, performed by second circuit 404,identifies a candidate point as corresponding to a redundant boundingbox to be removed in response to an IoU value satisfying (e.g., beinggreater than) an IoU threshold and a confidence score satisfying (e.g.,being less than) a confidence score of a neighboring point. In at leastone embodiment, first parallel suppression sub-process, performed bysecond circuit 404, can repeat calculations of IoU values and compareIoU values and confidence scores for each candidate point in a first setof candidate points that are within an area surrounding a respectivecandidate point. In at least one embodiment, first parallel suppressionsub-process, performed by second circuit 404, can only determine whethera respective candidate point corresponds to a redundant bounding box tobe removed and does not determine whether a neighboring candidate point,corresponding to a redundant bounding box, is to be removed. In at leastone embodiment, other parallel suppression sub-processes are performedfor neighboring candidate points to determine whether such neighboringcandidate points correspond to redundant bounding boxes. In at least oneembodiment, second parallel suppression sub-process, which is performedin connection with a second candidate point by third circuit 406, cancalculate an IoU value between second candidate point and a neighboringpoint, compare IoU value with a IoU threshold, and compare confidencescores in a similar manner to identify whether a second candidate pointcorresponds to a redundant bounding box to be removed. In at least oneembodiment, third parallel suppression sub-process, performed by fourthcircuit 408, and up to a 4th parallel suppression sub-process, performedby Nth circuit 410, can calculate IoU values and make similarcomparisons to identify one or more redundant bounding boxes to beremoved. In at least one embodiment, once a redundant bounding box isidentified by any of parallel suppression sub-processes, performed byparallel circuits 404-410, first circuit 402 can remove each redundantbounding box identified.

In at least one embodiment, a parallel NMS process that coordinatesoperations being parallelized is performed by first circuit 402 and afirst parallel suppression sub-process is performed on second circuit404. Similarly, in at least one embodiment, a second parallelsuppression sub-process is performed on third circuit 408, a thirdparallel suppression sub-process is performed on fourth circuit 408, andan Nth parallel suppression sub-process is performed on an Nth circuit410.

In at least one embodiment, method 400 can be implemented as an outputlayer of a neural network in which output feature map 401 is output fromone or more other layers. In at least one embodiment, method 400 is partof a first pipeline and an object detection task is performed in asecond pipeline. In at least one embodiment, method 400 is implementedas part an object detection task performed in a single pipeline.

In at least one embodiment, method 400 includes two or more parallelcircuits that perform two or more portions of a NMS algorithm inparallel to remove one or more redundant bounding boxes corresponding toone or more objects within one or more digital images. In at least oneembodiment, two or more parallel circuits are part of a processor. In atleast one embodiment, two or more parallel circuits are part of a set ofprocessors. In at least one embodiment, two or more parallel circuitsare part of a multi-GPU system. In at least one embodiment, each ofmultiple parallel circuits can be a GPU engine that can execute acompute kernel. In at least one embodiment, a compute kernel, which isalso referred to as a compute shader on a GPU, includes a routine thatis compiled for execution by a GPU, a DSP, an FPGA, or vectorprocessors, for example. In at least one embodiment, a compute kernelcorresponds to a loop (e.g., an inner loop) when implementing a parallelNMS algorithm. In at least one embodiment, each invocation of a computekernel within a batch is independent, allowing for data parallelexecution. In at least one embodiment, by using a compute kernel toperform a suppression sub-process only for an area surrounding acandidate point (and refraining from sorting indices of bounding boxesand handling bounding boxes in a descending order), performance of anNMS algorithm can be fully parallelized. For example, in at least oneembodiment, a parallel NMS process (e.g., a main process) is executed ona first processing circuit (e.g., CPU, GPU) or a first processingresource (e.g., execution thread) and parallel suppression sub-processesare executed as separate compute kernels on respective processingcircuits (e.g., GPUs) or separate processing resources (e.g., executionthreads). In at least one embodiment, compute kernels can be assigned toa set of GPUs that uses one or more parallel computing platforms and/orprogramming models (e.g., NVIDIA's CUDA model).

In at least one embodiment, a processor includes two or more parallelcircuits that perform operations of method 400 in order to perform twoor more portions of an NMS algorithm in parallel to remove one or moreredundant bounding boxes corresponding to one or more objects within oneor more digital images. In at least one embodiment, a processor includesone or more circuits to perform parallel suppression processes tosuppress one or more of a set of bounding boxes associated with anobject in an image by constraining an area that defines a subset ofbounding boxes for each suppression process. In at least one embodiment,a processor includes one or more circuits to perform operations ofmethod 400 in order to perform parallel NMS of candidate boxes for anobject detection task by constraining a search space to an areasurrounding a candidate bounding box. In at least one embodiment, aprocessor includes one or more circuits to suppress a bounding box foran object detection task based on comparisons with only one or morebounding boxes within an area surrounding a bounding box. In at leastone embodiment, a processor includes one or more circuits to detect anobject in an image using one or more neural networks that includes alayer, such as an output layer, to perform parallel NMS of boundingboxes. In at least one embodiment, a processor includes one or morecircuits to use one or more neural networks to generate a set ofbounding boxes in connection with an object detection task and performparallel NMS to remove one or more redundant bounding boxes using anoutput layer.

FIG. 5 illustrates a visual representation of a neural network 500 withmultiple layers 502 for object detection and a layer 504 for parallelNMS, according to at least one embodiment. In at least one embodiment,neural network 500 is performed by interference and/or training logic115. Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used in systemFIG. 10B for inferencing or predicting operations based, at least inpart, on weight parameters calculated using neural network trainingoperations, neural network functions and/or architectures, or neuralnetwork use cases described herein.

In at least one embodiment, neural network 500 obtains an input digitalimage 501 and multiple layers 502 process input digital image 501,outputting an output feature map 503. In at least one embodiment, outputfeature map 503 identifies multiple bounding boxes corresponding to anobject detected in input digital image 501. In at least one embodiment,output feature map 503 includes a confidence output header thatidentifies multiple bounding boxes. In at least one embodiment, outputfeature map 503 includes a confidence output header and a bounding boxregression header. In at least one embodiment, multiple layers 502 ofneural network 500 are part of a deep neural network (DNN) pipeline thatprovides output feature map 503 with multiple bounding boxes. In atleast one embodiment, layer 504 processes output feature map 503 toremove one or more redundant bounding boxes and provides a revisedoutput feature map 505. In at least one embodiment, output feature map505 includes a confidence output header and a bounding box regressionheader. In at least one embodiment, a confidence output header includesa heatmap of input digital image 501 in which point values are high ifthey belong to an object. In at least one embodiment, output feature map503 has a smaller resolution compared with input digital image 501. Forexample, in at least one embodiment where an input image is 800×600,output feature map 503 can be 200×150 with a stride of four. In at leastone embodiment, in order to obtain a full bounding box, in addition to aconfidence output header, a bounding box regression header can beemployed to work along with a confidence output header. In at least oneembodiment, four values can be used to describe a bounding box and alocation of a bounding box. For example, in at least one embodimentwhere a confidence output header is 200×150, a bounding box regressionheader can be 200×150×4 to be able to define a center point (x, y) and abox size (w, h), where x and y are coordinates of a center point and wand h are width and height of a bounding box. In at least oneembodiment, a bounding box regression header can be defined using otherrepresentations, such as left, top, right, and bottom corners or edgesof a bounding box (e.g., x1, y1, x2, y2). In at least one embodiment, aconfidence output header includes a confidence score for multiple pointsfrom which candidate points can be determined and a bounding boxregression header includes a bounding box description for each boundingbox corresponding to one or more objects detected by multiple layers 502within input digital image 501.

In at least one embodiment, output feature map 503 includes redundantbounding boxes, such as illustrated in digital image 601 of FIG. 6, andlayer 504 can perform parallel NMS to remove one or more redundantbounding boxes to obtain an output feature map 505, such as illustratedin image 612 of FIG. 6.

FIG. 6 illustrates a bounding box suppression process, according to atleast one embodiment. In at least one embodiment, digital image 601includes multiple bounding boxes 606 of an object (e.g., a dog) beforeparallel NMS is performed. In at least one embodiment, digital image 612includes a single bounding box 620 of an object after parallel NMS isperformed.

Referring back to FIG. 5, in at least one embodiment, layer 504 canperform other parallel clustering algorithms to suppress one or moreredundant bounding boxes to obtain output feature map 505. In at leastone embodiment, layer 504 can define a list of candidate bounding boxesby setting a confidence threshold, T, for a confidence output header. Inat least one embodiment, a confidence threshold T filters out boundingboxes with confidence values less than confidence threshold, T (e.g.,cov<T). In at least one embodiment, bounding boxes with confidencevalues greater than confidence threshold T (e.g., cov>T) can beidentified. As a result, in at least one embodiment, bounding boxes withappropriate confidence values can be stored in a list of bounding boxes,such as [bbox1, bbox2, bbox3 . . . bboxM], where M represents a positiveinteger representing a total number of bounding boxes contained inoutput feature map 503.

In at least one embodiment, one ground truth (GT) box can belong toseveral bounding boxes and several bounding boxes may need clustering toremove any redundant bounding box. In at least one embodiment, a degreeof overlap between two bounding boxes can be used for clusteringbounding boxes. In at least one embodiment, a degree of overlap isdetermined using an IoU value between two boxes by computing an area ofoverlap (also referred to as intersection) divided by an area of union,such as illustrated by equation 600 in FIG. 6. In at least oneembodiment, an IoU value is produced by equation 600 as area of overlap602 of two bounding boxes divided by an area of union 604 of these twobounding boxes.

Referring back to FIG. 5, in at least one embodiment, instead ofcomputing an IoU value between each pair of bounding boxes in outputfeature map 503, layer 504 can implement a parallel NMS algorithm to beperformed by two or more parallel circuits to remove redundant boundingboxes for an object detection pipeline, such as multiple layers 502 ofneural network 500. In at least one embodiment, an objective ofclustering is that for one object a most confident bounding box shouldbe identified and all redundant bounding boxes should be removed.Embodiments of redundant bounding box suppression as described hereincan be fully parallelized. Embodiments of parallel NMS as describedherein can reduce a number of IoU calculations while having only onestage and a lower complexity factor. Embodiments of parallel NMS asdescribed herein can be compatible with NMS optimizations, likeconfidence aggregation. Embodiments of parallel NMS as described hereincan be implemented as a layer (e.g., an output layer) of an ObjectDetection DNN pipeline and can be run on one or more GPUs without dataswitching between GPUs and a CPU.

In at least one embodiment, in a given confidence output feature map, aset of neighboring bounding boxes tend to gather around a center area.In at least one embodiment, a neural network with an object detectionpipeline can be trained with some loss techniques to ensure boundingboxes are gathered around a center area.

In at least one embodiment, for one output feature map F(M, N) for a 2Dconfidence output feature map where each point p∈F(M, N), there is onlyone box attached to this point. In at least one embodiment, neuralnetwork 500 can assign a parallel suppression process to considerwhether a bounding box itself should be deleted based on a confidencevalue comparison with bounding boxes belonging to neighboring points,instead of comparisons with all bounding boxes in an output feature map.

In at least one embodiment, a distance calculation can be a Euclideandistance calculation. In at least one embodiment, a distance calculationcan be a cosine distance calculation. In at least one embodiment, adistance calculation can be a formula as follows:

calc_dist:max[abs(x(p)−x(n)),abs(y(p)−y(n))], where “x(.)” and “y(.)”means position of output confidence feature map in x-axis and y-axisseparately.

Referring back to FIG. 5, in at least one embodiment, a main process oflayer 504 can launch a set of kernels (e.g., M×N) for parallelsuppression processes and each kernel handles one candidate point. In atleast one embodiment, each kernel's search space is constrained to anarea that defines a subset of neighboring bounding boxes, such asillustrated in FIG. 7. In at least one embodiment, a subset of a set ofkernels (M×N) can be utilized for parallel suppression processes andeach kernel can handle a valid candidate point that satisfies acriterion (e.g., equal to or greater than a lower threshold such as0.01).

FIG. 7 illustrates a reduced search space 700 for parallel NMS,according to at least one embodiment. In at least one embodiment,reduced search space 700 corresponds to one parallel suppression processas described herein. In at least one embodiment, reduced search space700, also referred to as bounding box area search space, defines asubset of bounding boxes to be evaluated for a given candidate point702. In at least one embodiment, an area of reduced search space 700constrains each of parallel suppression processes to only considerwhether candidate point 702 should be removed as being redundant basedon comparisons with only neighboring points within respective reducedsearch space 700.

In at least one embodiment, as illustrated in FIG. 7, a singleneighboring point 704 is within reduced search space 700 and asuppression process compares candidate point 702 to neighboring point704, including a confidence value comparison and an IoU comparison, asdescribed herein. In at least one embodiment, a suppression process(e.g., a kernel compute assigned to a first circuit) calculates an IoUvalue of candidate point 702 and neighboring point 704 and determineswhether an IoU value of candidate point 702 is greater than an IoUthreshold. In at least one embodiment, a suppression process (e.g., akernel compute assigned to a first circuit) determines whether aconfidence score of candidate point 702 is less than a confidence scoreof neighboring point 704. In at least one embodiment, a suppressionprocess identifies candidate point 702 as a redundant bounding box to beremoved responsive to an IoU value being greater than an IoU thresholdand a confidence score of candidate point 702 being less than aconfidence score of neighboring point 704. In at least one embodiment, asuppression process marks candidate point 702 as a redundant boundingbox to be deleted by a suppression process executing on another circuitor on a same circuit. In at least one embodiment, a suppression processidentifies candidate point 702 as not being a redundant bounding boxresponsive to either an IoU value being less than an IoU threshold or aconfidence score of candidate point 702 being greater than a confidencescore of neighboring point 704. In at least one embodiment, asillustrated in FIG. 7, reduced search space 700 includes only oneneighboring point 704 and only one IoU comparison and one confidencevalue comparison are performed, instead of IoU comparison and confidencevalue comparisons between all points.

In at least one embodiment, candidate point 702 can be a center point ofreduced search space 700. In at least one embodiment, reduced searchspace 700 can be defined as a rectangle, a square, a circle, or othershapes. In at least one embodiment, candidate point 702 and neighboringpoint 704 can be represented with x and y coordinates and acorresponding bounding box can be represented with x and y coordinatesand width w and height h. In at least one embodiment, candidate point702 and neighboring point 704 can be represented with polar coordinates.In at least one embodiment, reduced search space 700 is represented as abox with x and y coordinates, width w, and height h height. In at leastone embodiment, reduced search space 700 can be represented using otherdescriptors.

In at least one embodiment, neighboring point 704 is identified as beinglocated within reduced search space 700 by calculating a distancebetween candidate point 702 and neighboring point 704 in an outputfeature map. In at least one embodiment, a distance is calculated usinga Euclidean distance calculation. In at least one embodiment, a distanceis calculated using a cosine distance calculation. In at least oneembodiment, a distance is calculated using any distance calculationtechnique. In at least one embodiment, as illustrated in FIG. 7,neighboring point 704 is identified as a neighboring point or part of aset of neighboring points in reduced search space 700 responsive to adistance between neighboring point 704 and candidate point 702 beingless than a distance threshold. In at least one embodiment, a distancethreshold corresponds to an area of reduced search space 700 thatdefines a set of neighboring points for candidate point 702. In at leastone embodiment, a set of neighboring points can be identified as beinglocated within reduced search space 700 using other techniques.

In at least one embodiment, multiple parallel suppression processes canbe each initiated with respect to one of multiple candidate points forevaluation. In at least one embodiment, each of multiple parallelsuppression processes determines whether a respective candidate pointshould be removed as a redundant bounding box with respect toneighboring points located within a corresponding area defined by arespective search space. For example, in at least one embodiment, aparallel suppression process can be performed with respect to candidatepoint 702 and it can determine whether candidate point 702 correspondsto a redundant bounding box by comparing confidence values of candidatepoint 702 and neighboring point 704 and comparing an IoU value ofcorresponding bounding boxes with an IoU threshold, as illustrated inFIG. 7.

In at least one embodiment, each candidate point can be handledseparately, allowing suppression sub-processes to be fully parallelized.In at least one embodiment, a parallel NMS pipeline can be integrated aspart of an object detection pipeline, such as a layer of an objectdetection neural network. In at least one embodiment, a parallel NMSalgorithm can be integrated within or applied to an output of any objectdetection pipeline.

In at least one embodiment, a parallel NMS algorithm is applied to asingle confidence header feature map. In at least one embodiment, aparallel NMS algorithm is applied to multiple confidence header featuremaps. In at least one embodiment, an object detection pipeline can havemultiple output feature maps and a parallel NMS algorithm can performclustering for each feature map and then perform NMS on all boundingboxes. In at least one embodiment, an object detection pipeline can havemultiple output feature maps and candidate points can be mapped fromlow-resolution feature maps to high-resolution feature maps and then aparallel NMS algorithm can be performed on a largest feature map.

In at least one embodiment, a parallel NMS algorithm can be extended tomultiple anchor boxes for each point. In at least one embodiment, anchorboxes are a set of predefined bounding boxes of a certain height andwidth and a neural network can return a set of predictions for everyanchor box defined. In at least one embodiment, a parallel NMS algorithmidentifies a set of candidate boxes with a set of candidate points froman output feature map, where each point corresponds to at least a firstanchor box with a first confidence score and a second anchor box with asecond confidence score. In at least one embodiment, each box of a setof candidate boxes includes at least one of a first confidence scorethat is greater than a first confidence threshold or a second confidencescore that is greater than a second confidence threshold. In at leastone embodiment, a parallel NMS algorithm performs each of multipleparallel suppression processes in connection with one candidate point,and for each candidate point in one parallel suppression process, aparallel suppression process identifies at least one of a first set ofneighboring points that are within a first area associated with arespective candidate point or a second set of neighboring points thatare within a second area associated with a respective candidate point.In at least one embodiment, a compute kernel can be modified to includeanother loop to iterate through all bounding boxes for a currentcandidate point.

In at least one embodiment, a parallel NMS pipeline can be implementedin a GPU without switching to a CPU for sorting or handling boundingboxes in descending order. In at least one embodiment, a parallel NMSpipeline does not calculate a pairwise IoU values between all candidatebounding boxes, rather just between bounding boxes that are within aspecified area of a candidate bounding box being evaluated. In at leastone embodiment, a parallel NMS pipeline does not require explicitsorting and handling of bounding boxes in a particular order. In atleast one embodiment, a kernel of a parallel NMS pipeline is designedaccording to a 2D spatial position for each candidate bounding box,instead of a kernel that is designed according to box indices in amulti-stage process. In at least one embodiment, a parallel NMSalgorithm can be implemented in a single stage. In at least oneembodiment, a parallel NMS algorithm can be compatible with further NMSoptimizations, like confidence aggregation, as a kernel is designedaccording to a 2D spatial position for each candidate box, instead of akernel that is design according to box indices.

FIG. 8 is a flow diagram of a method 800 of performing parallel NMS,according to at least one embodiment. Method 800 can be performed byprocessing logic comprising hardware, software, firmware, or anycombination thereof. In at least one embodiment, method 800 is performedby interference and/or training logic 115. In at least one embodiment,method 800 is performed as part of a neural network, such as layer 504in neural network 500 of FIG. 5. Details regarding inference and/ortraining logic 115 are provided herein in conjunction with FIGS. 1Aand/or 1B. In at least one embodiment, inference and/or training logic115 may be used in system FIG. 10B for inferencing or predictingoperations based, at least in part, on weight parameters calculatedusing neural network training operations, neural network functionsand/or architectures, or neural network use cases described herein.

Referring back to FIG. 8, method 800 begins by processing logicidentifying a set of bounding boxes corresponding to one or more objectswithin one or more digital images (block 802). In at least oneembodiment, a set of bounding boxes are generated as a result of anobject detection pipeline, such as multiple layers 502 of neural network500 of FIG. 5. In at least one embodiment, a set of bounding boxes areidentified or included in an output feature map or a bounding boxregression header.

Referring back to FIG. 8, processing logic performs two or more portionsof a NMS algorithm in parallel to remove one or more redundant boundingboxes from a set of bounding boxes (block 804). In at least oneembodiment, at block 804, processing logic initiates multiple parallelsuppression processes to remove one or more redundant bounding boxescorresponding to one or more objects and defines an area that covers asubset of a set of bounding boxes for each suppression process. In atleast one embodiment at block 804, processing logic identifies a set ofcandidate points from an output feature map. In at least one embodiment,an output feature map includes a set of points where each pointcorresponds to a bounding box and includes a confidence score. In atleast one embodiment, each point of a set of candidate points includes aconfidence score that is greater than a confidence threshold. In atleast one embodiment, processing logic causes each of a set of parallelsuppression processes to be performed in connection with a respectivecandidate point. In at least one embodiment, for each candidate pointbeing evaluated by a parallel suppression process, each suppressionprocess identifies a set of neighboring points that are within an areaassociated with a respective candidate point.

In at least one embodiment, at block 804, processing logic calculates anIoU value of a respective candidate point and a neighboring point in anidentified set and determines whether an IoU value satisfies (e.g., isgreater than) an IoU threshold and a confidence score of a candidatepoint satisfies a criterion pertaining to (e.g., is less than) aconfidence score of a neighboring point. In at least one embodiment, atblock 804, processing logic identifies a candidate point as a redundantbounding box to be removed responsive to an IoU value satisfying an IoUthreshold and a confidence score of a candidate point satisfying acriterion pertaining to a confidence score of a neighboring point.

In at least one embodiment, at block 804, to identify a set of candidatepoints, processing logic calculates a distance between a respectivecandidate point and a second point in an output feature map. In at leastone embodiment, processing logic identifies a second point as aneighboring point responsive to a distance satisfying (e.g., being lessthan) a distance threshold. In at least one embodiment, a distancethreshold corresponds to an area associated with a respective candidatepoint. In at least one embodiment, processing logic calculates adistance using a Euclidean distance calculation between a candidatepoint and a second point. In at least one embodiment, processing logiccalculates a distance using a cosine distance calculation between acandidate point and a second point.

In at least one embodiment at block 804, processing logic identifies aset of candidate boxes from an output feature map including a pointcorresponding to a first anchor box with a first confidence score and asecond anchor box with a second confidence score. In at least oneembodiment, a first confidence score satisfies a first confidencethreshold and/or a second confidence score satisfies a second confidencethreshold. In at least one embodiment, processing logic performs each oftwo or more parallel suppression processes in connection with arespective candidate point, and for each candidate point in one parallelsuppression process, processing logic identifies at least one of a firstset of neighboring points that are within a first area associated arespective candidate point or a second set of neighboring points thatare within a second area associated with a respective candidate point.

Data Center

FIG. 9 illustrates an example data center 900, in which at least oneembodiment may be used. In at least one embodiment, data center 900includes a data center infrastructure layer 910, a framework layer 920,a software layer 930 and an application layer 940.

In at least one embodiment, as shown in FIG. 9, data centerinfrastructure layer 910 may include a resource orchestrator 912,grouped computing resources 914, and node computing resources (“nodeC.R.s”) 916(1)-916(N), where “N” represents a positive integer (whichmay be a different integer “N” than used in other figures). In at leastone embodiment, node C.R.s 916(1)-916(N) may include, but are notlimited to, any number of central processing units (“CPUs”) or otherprocessors (including accelerators, field programmable gate arrays(FPGAs), graphics processors, etc.), memory storage devices918(1)-918(N) (e.g., dynamic read-only memory, solid state storage ordisk drives), network input/output (“NW I/O”) devices, network switches,virtual machines (“VMs”), power modules, and cooling modules, etc. In atleast one embodiment, one or more node C.R.s from among node C.R.s916(1)-916(N) may be a server having one or more of above-mentionedcomputing resources.

In at least one embodiment, grouped computing resources 914 may includeseparate groupings of node C.R.s housed within one or more racks (notshown), or many racks housed in data centers at various geographicallocations (also not shown). In at least one embodiment, separategroupings of node C.R.s within grouped computing resources 914 mayinclude grouped compute, network, memory or storage resources that maybe configured or allocated to support one or more workloads. In at leastone embodiment, several node C.R.s including CPUs or processors maygrouped within one or more racks to provide compute resources to supportone or more workloads. In at least one embodiment, one or more racks mayalso include any number of power modules, cooling modules, and networkswitches, in any combination.

In at least one embodiment, resource orchestrator 912 may configure orotherwise control one or more node C.R.s 916(1)-916(N) and/or groupedcomputing resources 914. In at least one embodiment, resourceorchestrator 912 may include a software design infrastructure (“SDI”)management entity for data center 900. In at least one embodiment,resource orchestrator 112 may include hardware, software or somecombination thereof.

In at least one embodiment, as shown in FIG. 9, framework layer 920includes a job scheduler 922, a configuration manager 924, a resourcemanager 926 and a distributed file system 928. In at least oneembodiment, framework layer 920 may include a framework to supportsoftware 932 of software layer 930 and/or one or more application(s) 942of application layer 940. In at least one embodiment, software 932 orapplication(s) 942 may respectively include web-based service softwareor applications, such as those provided by Amazon Web Services, GoogleCloud and Microsoft Azure. In at least one embodiment, framework layer920 may be, but is not limited to, a type of free and open-sourcesoftware web application framework such as Apache Spark™ (hereinafter“Spark”) that may utilize distributed file system 928 for large-scaledata processing (e.g., “big data”). In at least one embodiment, jobscheduler 922 may include a Spark driver to facilitate scheduling ofworkloads supported by various layers of data center 900. In at leastone embodiment, configuration manager 924 may be capable of configuringdifferent layers such as software layer 930 and framework layer 920including Spark and distributed file system 928 for supportinglarge-scale data processing. In at least one embodiment, resourcemanager 926 may be capable of managing clustered or grouped computingresources mapped to or allocated for support of distributed file system928 and job scheduler 922. In at least one embodiment, clustered orgrouped computing resources may include grouped computing resources 914at data center infrastructure layer 910. In at least one embodiment,resource manager 926 may coordinate with resource orchestrator 912 tomanage these mapped or allocated computing resources.

In at least one embodiment, software 932 included in software layer 930may include software used by at least portions of node C.R.s916(1)-916(N), grouped computing resources 914, and/or distributed filesystem 928 of framework layer 920. In at least one embodiment, one ormore types of software may include, but are not limited to, Internet webpage search software, e-mail virus scan software, database software, andstreaming video content software.

In at least one embodiment, application(s) 942 included in applicationlayer 940 may include one or more types of applications used by at leastportions of node C.R.s 916(1)-916(N), grouped computing resources 914,and/or distributed file system 928 of framework layer 920. In at leastone embodiment, one or more types of applications may include, but arenot limited to, any number of a genomics application, a cognitivecompute, application and a machine learning application, includingtraining or inferencing software, machine learning framework software(e.g., PyTorch, TensorFlow, Caffe, etc.) or other machine learningapplications used in conjunction with one or more embodiments.

In at least one embodiment, any of configuration manager 924, resourcemanager 926, and resource orchestrator 912 may implement any number andtype of self-modifying actions based on any amount and type of dataacquired in any technically feasible fashion. In at least oneembodiment, self-modifying actions may relieve a data center operator ofdata center 900 from making possibly bad configuration decisions andpossibly avoiding underutilized and/or poor performing portions of adata center.

In at least one embodiment, data center 900 may include tools, services,software or other resources to train one or more machine learning modelsor predict or infer information using one or more machine learningmodels according to one or more embodiments described herein. Forexample, in at least one embodiment, a machine learning model may betrained by calculating weight parameters according to a neural networkarchitecture using software and computing resources described above withrespect to data center 900. In at least one embodiment, trained machinelearning models corresponding to one or more neural networks may be usedto infer or predict information using resources described above withrespect to data center 900 by using weight parameters calculated throughone or more training techniques described herein.

In at least one embodiment, data center may use CPUs,application-specific integrated circuits (ASICs), GPUs, FPGAs, or otherhardware to perform training and/or inferencing using above-describedresources. Moreover, one or more software and/or hardware resourcesdescribed above may be configured as a service to allow users to trainor performing inferencing of information, such as image recognition,speech recognition, or other artificial intelligence services.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used in systemFIG. 9 for inferencing or predicting operations based, at least in part,on weight parameters calculated using neural network trainingoperations, neural network functions and/or architectures, or neuralnetwork use cases described herein.

Autonomous Vehicle

FIG. 10A illustrates an example of an autonomous vehicle 1000, accordingto at least one embodiment. In at least one embodiment, autonomousvehicle 1000 (alternatively referred to herein as “vehicle 1000”) maybe, without limitation, a passenger vehicle, such as a car, a truck, abus, and/or another type of vehicle that accommodates one or morepassengers. In at least one embodiment, vehicle 1000 may be asemi-tractor-trailer truck used for hauling cargo. In at least oneembodiment, vehicle 1000 may be an airplane, robotic vehicle, or otherkind of vehicle.

Autonomous vehicles may be described in terms of automation levels,defined by National Highway Traffic Safety Administration (“NHTSA”), adivision of US Department of Transportation, and Society of AutomotiveEngineers (“SAE”) “Taxonomy and Definitions for Terms Related to DrivingAutomation Systems for On-Road Motor Vehicles” (e.g., Standard No.J3016-201806, published on Jun. 15, 2018, Standard No. J3016-201609,published on Sep. 30, 2016, and previous and future versions of thisstandard). In at least one embodiment, vehicle 1000 may be capable offunctionality in accordance with one or more of Level 1 through Level 5of autonomous driving levels. For example, in at least one embodiment,vehicle 1000 may be capable of conditional automation (Level 3), highautomation (Level 4), and/or full automation (Level 5), depending onembodiment.

In at least one embodiment, vehicle 1000 may include, withoutlimitation, components such as a chassis, a vehicle body, wheels (e.g.,2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle.In at least one embodiment, vehicle 1000 may include, withoutlimitation, a propulsion system 1050, such as an internal combustionengine, hybrid electric power plant, an all-electric engine, and/oranother propulsion system type. In at least one embodiment, propulsionsystem 1050 may be connected to a drive train of vehicle 1000, which mayinclude, without limitation, a transmission, to enable propulsion ofvehicle 1000. In at least one embodiment, propulsion system 1050 may becontrolled in response to receiving signals from athrottle/accelerator(s) 1052.

In at least one embodiment, a steering system 1054, which may include,without limitation, a steering wheel, is used to steer vehicle 1000(e.g., along a desired path or route) when propulsion system 1050 isoperating (e.g., when vehicle 1000 is in motion). In at least oneembodiment, steering system 1054 may receive signals from steeringactuator(s) 1056. In at least one embodiment, a steering wheel may beoptional for full automation (Level 5) functionality. In at least oneembodiment, a brake sensor system 1046 may be used to operate vehiclebrakes in response to receiving signals from brake actuator(s) 1048and/or brake sensors.

In at least one embodiment, controller(s) 1036, which may include,without limitation, one or more system on chips (“SoCs”) (not shown inFIG. 10A) and/or graphics processing unit(s) (“GPU(s)”), provide signals(e.g., representative of commands) to one or more components and/orsystems of vehicle 1000. For instance, in at least one embodiment,controller(s) 1036 may send signals to operate vehicle brakes via brakeactuator(s) 1048, to operate steering system 1054 via steeringactuator(s) 1056, to operate propulsion system 1050 viathrottle/accelerator(s) 1052. In at least one embodiment, controller(s)1036 may include one or more onboard (e.g., integrated) computingdevices that process sensor signals, and output operation commands(e.g., signals representing commands) to enable autonomous drivingand/or to assist a human driver in driving vehicle 1000. In at least oneembodiment, controller(s) 1036 may include a first controller forautonomous driving functions, a second controller for functional safetyfunctions, a third controller for artificial intelligence functionality(e.g., computer vision), a fourth controller for infotainmentfunctionality, a fifth controller for redundancy in emergencyconditions, and/or other controllers. In at least one embodiment, asingle controller may handle two or more of above functionalities, twoor more controllers may handle a single functionality, and/or anycombination thereof.

In at least one embodiment, controller(s) 1036 provide signals forcontrolling one or more components and/or systems of vehicle 1000 inresponse to sensor data received from one or more sensors (e.g., sensorinputs). In at least one embodiment, sensor data may be received from,for example and without limitation, global navigation satellite systems(“GNSS”) sensor(s) 1058 (e.g., Global Positioning System sensor(s)),RADAR sensor(s) 1060, ultrasonic sensor(s) 1062, LIDAR sensor(s) 1064,inertial measurement unit (“IMU”) sensor(s) 1066 (e.g.,accelerometer(s), gyroscope(s), a magnetic compass or magneticcompasses, magnetometer(s), etc.), microphone(s) 1096, stereo camera(s)1068, wide-view camera(s) 1070 (e.g., fisheye cameras), infraredcamera(s) 1072, surround camera(s) 1074 (e.g., 360 degree cameras),long-range cameras (not shown in FIG. 10A), mid-range camera(s) (notshown in FIG. 10A), speed sensor(s) 1044 (e.g., for measuring speed ofvehicle 1000), vibration sensor(s) 1042, steering sensor(s) 1040, brakesensor(s) (e.g., as part of brake sensor system 1046), and/or othersensor types.

In at least one embodiment, one or more of controller(s) 1036 mayreceive inputs (e.g., represented by input data) from an instrumentcluster 1032 of vehicle 1000 and provide outputs (e.g., represented byoutput data, display data, etc.) via a human-machine interface (“HMI”)display 1034, an audible annunciator, a loudspeaker, and/or via othercomponents of vehicle 1000. In at least one embodiment, outputs mayinclude information such as vehicle velocity, speed, time, map data(e.g., a High Definition map (not shown in FIG. 10A), location data(e.g., vehicle's 1000 location, such as on a map), direction, locationof other vehicles (e.g., an occupancy grid), information about objectsand status of objects as perceived by controller(s) 1036, etc. Forexample, in at least one embodiment, HMI display 1034 may displayinformation about presence of one or more objects (e.g., a street sign,caution sign, traffic light changing, etc.), and/or information aboutdriving maneuvers vehicle has made, is making, or will make (e.g.,changing lanes now, taking exit 34B in two miles, etc.).

In at least one embodiment, vehicle 1000 further includes a networkinterface 1024 which may use wireless antenna(s) 1026 and/or modem(s) tocommunicate over one or more networks. For example, in at least oneembodiment, network interface 1024 may be capable of communication overLong-Term Evolution (“LTE”), Wideband Code Division Multiple Access(“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), GlobalSystem for Mobile communication (“GSM”), IMT-CDMA Multi-Carrier(“CDMA2000”) networks, etc. In at least one embodiment, wirelessantenna(s) 1026 may also enable communication between objects inenvironment (e.g., vehicles, mobile devices, etc.), using local areanetwork(s), such as Bluetooth, Bluetooth Low Energy (“LE”), Z-Wave,ZigBee, etc., and/or low power wide-area network(s) (“LPWANs”), such asLoRaWAN, SigFox, etc. protocols.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used in systemFIG. 10A for inferencing or predicting operations based, at least inpart, on weight parameters calculated using neural network trainingoperations, neural network functions and/or architectures, or neuralnetwork use cases described herein.

FIG. 10B illustrates an example of camera locations and fields of viewfor autonomous vehicle 1000 of FIG. 10A, according to at least oneembodiment. In at least one embodiment, cameras and respective fields ofview are one example embodiment and are not intended to be limiting. Forinstance, in at least one embodiment, additional and/or alternativecameras may be included and/or cameras may be located at differentlocations on vehicle 1000.

In at least one embodiment, camera types for cameras may include, butare not limited to, digital cameras that may be adapted for use withcomponents and/or systems of vehicle 1000. In at least one embodiment,camera(s) may operate at automotive safety integrity level (“ASIL”) Band/or at another ASIL. In at least one embodiment, camera types may becapable of any image capture rate, such as 60 frames per second (fps),1220 fps, 240 fps, etc., depending on embodiment. In at least oneembodiment, cameras may be capable of using rolling shutters, globalshutters, another type of shutter, or a combination thereof. In at leastone embodiment, color filter array may include a red clear clear clear(“RCCC”) color filter array, a red clear clear blue (“RCCB”) colorfilter array, a red blue green clear (“RBGC”) color filter array, aFoveon X3 color filter array, a Bayer sensors (“RGGB”) color filterarray, a monochrome sensor color filter array, and/or another type ofcolor filter array. In at least one embodiment, clear pixel cameras,such as cameras with an RCCC, an RCCB, and/or an RBGC color filterarray, may be used in an effort to increase light sensitivity.

In at least one embodiment, one or more of camera(s) may be used toperform advanced driver assistance systems (“ADAS”) functions (e.g., aspart of a redundant or fail-safe design). For example, in at least oneembodiment, a Multi-Function Mono Camera may be installed to providefunctions including lane departure warning, traffic sign assist andintelligent headlamp control. In at least one embodiment, one or more ofcamera(s) (e.g., all cameras) may record and provide image data (e.g.,video) simultaneously.

In at least one embodiment, one or more camera may be mounted in amounting assembly, such as a custom designed (three-dimensional (“3D”)printed) assembly, in order to cut out stray light and reflections fromwithin vehicle 1000 (e.g., reflections from dashboard reflected inwindshield mirrors) which may interfere with camera image data captureabilities. With reference to wing-mirror mounting assemblies, in atleast one embodiment, wing-mirror assemblies may be custom 3D printed sothat a camera mounting plate matches a shape of a wing-mirror. In atleast one embodiment, camera(s) may be integrated into wing-mirrors. Inat least one embodiment, for side-view cameras, camera(s) may also beintegrated within four pillars at each corner of a cabin.

In at least one embodiment, cameras with a field of view that includeportions of an environment in front of vehicle 1000 (e.g., front-facingcameras) may be used for surround view, to help identify forward facingpaths and obstacles, as well as aid in, with help of one or more ofcontroller(s) 1036 and/or control SoCs, providing information criticalto generating an occupancy grid and/or determining preferred vehiclepaths. In at least one embodiment, front-facing cameras may be used toperform many similar ADAS functions as LIDAR, including, withoutlimitation, emergency braking, pedestrian detection, and collisionavoidance. In at least one embodiment, front-facing cameras may also beused for ADAS functions and systems including, without limitation, LaneDeparture Warnings (“LDW”), Autonomous Cruise Control (“ACC”), and/orother functions such as traffic sign recognition.

In at least one embodiment, a variety of cameras may be used in afront-facing configuration, including, for example, a monocular cameraplatform that includes a CMOS (“complementary metal oxidesemiconductor”) color imager. In at least one embodiment, a wide-viewcamera 1070 may be used to perceive objects coming into view from aperiphery (e.g., pedestrians, crossing traffic or bicycles). Althoughonly one wide-view camera 1070 is illustrated in FIG. 10B, in otherembodiments, there may be any number (including zero) wide-view camerason vehicle 1000. In at least one embodiment, any number of long-rangecamera(s) 1098 (e.g., a long-view stereo camera pair) may be used fordepth-based object detection, especially for objects for which a neuralnetwork has not yet been trained. In at least one embodiment, long-rangecamera(s) 1098 may also be used for object detection and classification,as well as basic object tracking.

In at least one embodiment, any number of stereo camera(s) 1068 may alsobe included in a front-facing configuration. In at least one embodiment,one or more of stereo camera(s) 1068 may include an integrated controlunit comprising a scalable processing unit, which may provide aprogrammable logic (“FPGA”) and a multi-core micro-processor with anintegrated Controller Area Network (“CAN”) or Ethernet interface on asingle chip. In at least one embodiment, such a unit may be used togenerate a 3D map of an environment of vehicle 1000, including adistance estimate for all points in an image. In at least oneembodiment, one or more of stereo camera(s) 1068 may include, withoutlimitation, compact stereo vision sensor(s) that may include, withoutlimitation, two camera lenses (one each on left and right) and an imageprocessing chip that may measure distance from vehicle 1000 to targetobject and use generated information (e.g., metadata) to activateautonomous emergency braking and lane departure warning functions. In atleast one embodiment, other types of stereo camera(s) 1068 may be usedin addition to, or alternatively from, those described herein.

In at least one embodiment, cameras with a field of view that includeportions of environment to sides of vehicle 1000 (e.g., side-viewcameras) may be used for surround view, providing information used tocreate and update an occupancy grid, as well as to generate side impactcollision warnings. For example, in at least one embodiment, surroundcamera(s) 1074 (e.g., four surround cameras as illustrated in FIG. 10B)could be positioned on vehicle 1000. In at least one embodiment,surround camera(s) 1074 may include, without limitation, any number andcombination of wide-view cameras, fisheye camera(s), 360 degreecamera(s), and/or similar cameras. For instance, in at least oneembodiment, four fisheye cameras may be positioned on a front, a rear,and sides of vehicle 1000. In at least one embodiment, vehicle 1000 mayuse three surround camera(s) 1074 (e.g., left, right, and rear), and mayleverage one or more other camera(s) (e.g., a forward-facing camera) asa fourth surround-view camera.

In at least one embodiment, cameras with a field of view that includeportions of an environment behind vehicle 1000 (e.g., rear-view cameras)may be used for parking assistance, surround view, rear collisionwarnings, and creating and updating an occupancy grid. In at least oneembodiment, a wide variety of cameras may be used including, but notlimited to, cameras that are also suitable as a front-facing camera(s)(e.g., long-range cameras 1098 and/or mid-range camera(s) 1076, stereocamera(s) 1068), infrared camera(s) 1072, etc.), as described herein.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used in systemFIG. 10B for inferencing or predicting operations based, at least inpart, on weight parameters calculated using neural network trainingoperations, neural network functions and/or architectures, or neuralnetwork use cases described herein.

FIG. 10C is a block diagram illustrating an example system architecturefor autonomous vehicle 1000 of FIG. 10A, according to at least oneembodiment. In at least one embodiment, each of components, features,and systems of vehicle 1000 in FIG. 10C is illustrated as beingconnected via a bus 1002. In at least one embodiment, bus 1002 mayinclude, without limitation, a CAN data interface (alternativelyreferred to herein as a “CAN bus”). In at least one embodiment, a CANmay be a network inside vehicle 1000 used to aid in control of variousfeatures and functionality of vehicle 1000, such as actuation of brakes,acceleration, braking, steering, windshield wipers, etc. In at least oneembodiment, bus 1002 may be configured to have dozens or even hundredsof nodes, each with its own unique identifier (e.g., a CAN ID). In atleast one embodiment, bus 1002 may be read to find steering wheel angle,ground speed, engine revolutions per minute (“RPMs”), button positions,and/or other vehicle status indicators. In at least one embodiment, bus1002 may be a CAN bus that is ASIL B compliant.

In at least one embodiment, in addition to, or alternatively from CAN,FlexRay and/or Ethernet protocols may be used. In at least oneembodiment, there may be any number of busses forming bus 1002, whichmay include, without limitation, zero or more CAN busses, zero or moreFlexRay busses, zero or more Ethernet busses, and/or zero or more othertypes of busses using different protocols. In at least one embodiment,two or more busses may be used to perform different functions, and/ormay be used for redundancy. For example, a first bus may be used forcollision avoidance functionality and a second bus may be used foractuation control. In at least one embodiment, each bus of bus 1002 maycommunicate with any of components of vehicle 1000, and two or morebusses of bus 1002 may communicate with corresponding components. In atleast one embodiment, each of any number of system(s) on chip(s)(“SoC(s)”) 1004 (such as SoC 1004(A) and SoC 1004(B), each ofcontroller(s) 1036, and/or each computer within vehicle may have accessto same input data (e.g., inputs from sensors of vehicle 1000), and maybe connected to a common bus, such CAN bus.

In at least one embodiment, vehicle 1000 may include one or morecontroller(s) 1036, such as those described herein with respect to FIG.10A. In at least one embodiment, controller(s) 1036 may be used for avariety of functions. In at least one embodiment, controller(s) 1036 maybe coupled to any of various other components and systems of vehicle1000, and may be used for control of vehicle 1000, artificialintelligence of vehicle 1000, infotainment for vehicle 1000, and/orother functions.

In at least one embodiment, vehicle 1000 may include any number of SoCs1004. In at least one embodiment, each of SoCs 1004 may include, withoutlimitation, central processing units (“CPU(s)”) 1006, graphicsprocessing units (“GPU(s)”) 1008, processor(s) 1010, cache(s) 1012,accelerator(s) 1014, data store(s) 1016, and/or other components andfeatures not illustrated. In at least one embodiment, SoC(s) 1004 may beused to control vehicle 1000 in a variety of platforms and systems. Forexample, in at least one embodiment, SoC(s) 1004 may be combined in asystem (e.g., system of vehicle 1000) with a High Definition (“HD”) map1022 which may obtain map refreshes and/or updates via network interface1024 from one or more servers (not shown in FIG. 10C).

In at least one embodiment, CPU(s) 1006 may include a CPU cluster or CPUcomplex (alternatively referred to herein as a “CCPLEX”). In at leastone embodiment, CPU(s) 1006 may include multiple cores and/or level two(“L2”) caches. For instance, in at least one embodiment, CPU(s) 1006 mayinclude eight cores in a coherent multi-processor configuration. In atleast one embodiment, CPU(s) 1006 may include four dual-core clusterswhere each cluster has a dedicated L2 cache (e.g., a 2 megabyte (MB) L2cache). In at least one embodiment, CPU(s) 1006 (e.g., CCPLEX) may beconfigured to support simultaneous cluster operations enabling anycombination of clusters of CPU(s) 1006 to be active at any given time.

In at least one embodiment, one or more of CPU(s) 1006 may implementpower management capabilities that include, without limitation, one ormore of following features: individual hardware blocks may beclock-gated automatically when idle to save dynamic power; each coreclock may be gated when such core is not actively executing instructionsdue to execution of Wait for Interrupt (“WFI”)/Wait for Event (“WFE”)instructions; each core may be independently power-gated; each corecluster may be independently clock-gated when all cores are clock-gatedor power-gated; and/or each core cluster may be independentlypower-gated when all cores are power-gated. In at least one embodiment,CPU(s) 1006 may further implement an enhanced algorithm for managingpower states, where allowed power states and expected wakeup times arespecified, and hardware/microcode determines which best power state toenter for core, cluster, and CCPLEX. In at least one embodiment,processing cores may support simplified power state entry sequences insoftware with work offloaded to microcode.

In at least one embodiment, GPU(s) 1008 may include an integrated GPU(alternatively referred to herein as an “iGPU”). In at least oneembodiment, GPU(s) 1008 may be programmable and may be efficient forparallel workloads. In at least one embodiment, GPU(s) 1008 may use anenhanced tensor instruction set. In at least one embodiment, GPU(s) 1008may include one or more streaming microprocessors, where each streamingmicroprocessor may include a level one (“L1”) cache (e.g., an L1 cachewith at least 96 KB storage capacity), and two or more streamingmicroprocessors may share an L2 cache (e.g., an L2 cache with a 512 KBstorage capacity). In at least one embodiment, GPU(s) 1008 may includeat least eight streaming microprocessors. In at least one embodiment,GPU(s) 1008 may use compute application programming interface(s)(API(s)). In at least one embodiment, GPU(s) 1008 may use one or moreparallel computing platforms and/or programming models (e.g., NVIDIA'sCUDA model).

In at least one embodiment, one or more of GPU(s) 1008 may bepower-optimized for best performance in automotive and embedded usecases. For example, in at least one embodiment, GPU(s) 1008 could befabricated on Fin field-effect transistor (“FinFET”) circuitry. In atleast one embodiment, each streaming microprocessor may incorporate anumber of mixed-precision processing cores partitioned into multipleblocks. For example, and without limitation, 64 PF32 cores and 32 PF64cores could be partitioned into four processing blocks. In at least oneembodiment, each processing block could be allocated 16 FP32 cores, 8FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores fordeep learning matrix arithmetic, a level zero (“L0”) instruction cache,a warp scheduler, a dispatch unit, and/or a 64 KB register file. In atleast one embodiment, streaming microprocessors may include independentparallel integer and floating-point data paths to provide for efficientexecution of workloads with a mix of computation and addressingcalculations. In at least one embodiment, streaming microprocessors mayinclude independent thread scheduling capability to enable finer-grainsynchronization and cooperation between parallel threads. In at leastone embodiment, streaming microprocessors may include a combined L1 datacache and shared memory unit in order to improve performance whilesimplifying programming.

In at least one embodiment, one or more of GPU(s) 1008 may include ahigh bandwidth memory (“HBM) and/or a 16 GB high-bandwidth memory secondgeneration (“HBM2”) memory subsystem to provide, in some examples, about900 GB/second peak memory bandwidth. In at least one embodiment, inaddition to, or alternatively from, HBM memory, a synchronous graphicsrandom-access memory (“SGRAM”) may be used, such as a graphics doubledata rate type five synchronous random-access memory (“GDDR5”).

In at least one embodiment, GPU(s) 1008 may include unified memorytechnology. In at least one embodiment, address translation services(“ATS”) support may be used to allow GPU(s) 1008 to access CPU(s) 1006page tables directly. In at least one embodiment, embodiment, when a GPUof GPU(s) 1008 memory management unit (“MMU”) experiences a miss, anaddress translation request may be transmitted to CPU(s) 1006. Inresponse, 2 CPU of CPU(s) 1006 may look in its page tables for avirtual-to-physical mapping for an address and transmit translation backto GPU(s) 1008, in at least one embodiment. In at least one embodiment,unified memory technology may allow a single unified virtual addressspace for memory of both CPU(s) 1006 and GPU(s) 1008, therebysimplifying GPU(s) 1008 programming and porting of applications toGPU(s) 1008.

In at least one embodiment, GPU(s) 1008 may include any number of accesscounters that may keep track of frequency of access of GPU(s) 1008 tomemory of other processors. In at least one embodiment, accesscounter(s) may help ensure that memory pages are moved to physicalmemory of a processor that is accessing pages most frequently, therebyimproving efficiency for memory ranges shared between processors.

In at least one embodiment, one or more of SoC(s) 1004 may include anynumber of cache(s) 1012, including those described herein. For example,in at least one embodiment, cache(s) 1012 could include a level three(“L3”) cache that is available to both CPU(s) 1006 and GPU(s) 1008(e.g., that is connected to CPU(s) 1006 and GPU(s) 1008). In at leastone embodiment, cache(s) 1012 may include a write-back cache that maykeep track of states of lines, such as by using a cache coherenceprotocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, a L3cache may include 4 MB of memory or more, depending on embodiment,although smaller cache sizes may be used.

In at least one embodiment, one or more of SoC(s) 1004 may include oneor more accelerator(s) 1014 (e.g., hardware accelerators, softwareaccelerators, or a combination thereof). In at least one embodiment,SoC(s) 1004 may include a hardware acceleration cluster that may includeoptimized hardware accelerators and/or large on-chip memory. In at leastone embodiment, large on-chip memory (e.g., 4 MB of SRAM), may enable ahardware acceleration cluster to accelerate neural networks and othercalculations. In at least one embodiment, a hardware accelerationcluster may be used to complement GPU(s) 1008 and to off-load some oftasks of GPU(s) 1008 (e.g., to free up more cycles of GPU(s) 1008 forperforming other tasks). In at least one embodiment, accelerator(s) 1014could be used for targeted workloads (e.g., perception, convolutionalneural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.) thatare stable enough to be amenable to acceleration. In at least oneembodiment, a CNN may include a region-based or regional convolutionalneural networks (“RCNNs”) and Fast RCNNs (e.g., as used for objectdetection) or other type of CNN.

In at least one embodiment, accelerator(s) 1014 (e.g., hardwareacceleration cluster) may include one or more deep learning accelerator(“DLA”). In at least one embodiment, DLA(s) may include, withoutlimitation, one or more Tensor processing units (“TPUs”) that may beconfigured to provide an additional ten trillion operations per secondfor deep learning applications and inferencing. In at least oneembodiment, TPUs may be accelerators configured to, and optimized for,performing image processing functions (e.g., for CNNs, RCNNs, etc.). Inat least one embodiment, DLA(s) may further be optimized for a specificset of neural network types and floating point operations, as well asinferencing. In at least one embodiment, design of DLA(s) may providemore performance per millimeter than a typical general-purpose GPU, andtypically vastly exceeds performance of a CPU. In at least oneembodiment, TPU(s) may perform several functions, including asingle-instance convolution function, supporting, for example, INT8,INT16, and FP16 data types for both features and weights, as well aspost-processor functions. In at least one embodiment, DLA(s) may quicklyand efficiently execute neural networks, especially CNNs, on processedor unprocessed data for any of a variety of functions, including, forexample and without limitation: a CNN for object identification anddetection using data from camera sensors; a CNN for distance estimationusing data from camera sensors; a CNN for emergency vehicle detectionand identification and detection using data from microphones; a CNN forfacial recognition and vehicle owner identification using data fromcamera sensors; and/or a CNN for security and/or safety related events.

In at least one embodiment, DLA(s) may perform any function of GPU(s)1008, and by using an inference accelerator, for example, a designer maytarget either DLA(s) or GPU(s) 1008 for any function. For example, in atleast one embodiment, a designer may focus processing of CNNs andfloating point operations on DLA(s) and leave other functions to GPU(s)1008 and/or accelerator(s) 1014.

In at least one embodiment, accelerator(s) 1014 may include programmablevision accelerator (“PVA”), which may alternatively be referred toherein as a computer vision accelerator. In at least one embodiment, PVAmay be designed and configured to accelerate computer vision algorithmsfor advanced driver assistance system (“ADAS”) 1038, autonomous driving,augmented reality (“AR”) applications, and/or virtual reality (“VR”)applications. In at least one embodiment, PVA may provide a balancebetween performance and flexibility. For example, in at least oneembodiment, each PVA may include, for example and without limitation,any number of reduced instruction set computer (“RISC”) cores, directmemory access (“DMA”), and/or any number of vector processors.

In at least one embodiment, RISC cores may interact with image sensors(e.g., image sensors of any cameras described herein), image signalprocessor(s), etc. In at least one embodiment, each RISC core mayinclude any amount of memory. In at least one embodiment, RISC cores mayuse any of a number of protocols, depending on embodiment. In at leastone embodiment, RISC cores may execute a real-time operating system(“RTOS”). In at least one embodiment, RISC cores may be implementedusing one or more integrated circuit devices, application specificintegrated circuits (“ASICs”), and/or memory devices. For example, in atleast one embodiment, RISC cores could include an instruction cacheand/or a tightly coupled RAM.

In at least one embodiment, DMA may enable components of PVA to accesssystem memory independently of CPU(s) 1006. In at least one embodiment,DMA may support any number of features used to provide optimization to aPVA including, but not limited to, supporting multi-dimensionaladdressing and/or circular addressing. In at least one embodiment, DMAmay support up to six or more dimensions of addressing, which mayinclude, without limitation, block width, block height, block depth,horizontal block stepping, vertical block stepping, and/or depthstepping.

In at least one embodiment, vector processors may be programmableprocessors that may be designed to efficiently and flexibly executeprogramming for computer vision algorithms and provide signal processingcapabilities. In at least one embodiment, a PVA may include a PVA coreand two vector processing subsystem partitions. In at least oneembodiment, a PVA core may include a processor subsystem, DMA engine(s)(e.g., two DMA engines), and/or other peripherals. In at least oneembodiment, a vector processing subsystem may operate as a primaryprocessing engine of a PVA, and may include a vector processing unit(“VPU”), an instruction cache, and/or vector memory (e.g., “VMEM”). Inat least one embodiment, VPU core may include a digital signal processorsuch as, for example, a single instruction, multiple data (“SIMD”), verylong instruction word (“VLIW”) digital signal processor. In at least oneembodiment, a combination of SIMD and VLIW may enhance throughput andspeed.

In at least one embodiment, each of vector processors may include aninstruction cache and may be coupled to dedicated memory. As a result,in at least one embodiment, each of vector processors may be configuredto execute independently of other vector processors. In at least oneembodiment, vector processors that are included in a particular PVA maybe configured to employ data parallelism. For instance, in at least oneembodiment, plurality of vector processors included in a single PVA mayexecute a common computer vision algorithm, but on different regions ofan image. In at least one embodiment, vector processors included in aparticular PVA may simultaneously execute different computer visionalgorithms, on one image, or even execute different algorithms onsequential images or portions of an image. In at least one embodiment,among other things, any number of PVAs may be included in hardwareacceleration cluster and any number of vector processors may be includedin each PVA. In at least one embodiment, PVA may include additionalerror correcting code (“ECC”) memory, to enhance overall system safety.

In at least one embodiment, accelerator(s) 1014 may include a computervision network on-chip and static random-access memory (“SRAM”), forproviding a high-bandwidth, low latency SRAM for accelerator(s) 1014. Inat least one embodiment, on-chip memory may include at least 4 MB SRAM,comprising, for example and without limitation, eight field-configurablememory blocks, that may be accessible by both a PVA and a DLA. In atleast one embodiment, each pair of memory blocks may include an advancedperipheral bus (“APB”) interface, configuration circuitry, a controller,and a multiplexer. In at least one embodiment, any type of memory may beused. In at least one embodiment, a PVA and a DLA may access memory viaa backbone that provides a PVA and a DLA with high-speed access tomemory. In at least one embodiment, a backbone may include a computervision network on-chip that interconnects a PVA and a DLA to memory(e.g., using APB).

In at least one embodiment, a computer vision network on-chip mayinclude an interface that determines, before transmission of any controlsignal/address/data, that both a PVA and a DLA provide ready and validsignals. In at least one embodiment, an interface may provide forseparate phases and separate channels for transmitting controlsignals/addresses/data, as well as burst-type communications forcontinuous data transfer. In at least one embodiment, an interface maycomply with International Organization for Standardization (“ISO”) 26262or International Electrotechnical Commission (“IEC”) 61508 standards,although other standards and protocols may be used.

In at least one embodiment, one or more of SoC(s) 1004 may include areal-time ray-tracing hardware accelerator. In at least one embodiment,real-time ray-tracing hardware accelerator may be used to quickly andefficiently determine positions and extents of objects (e.g., within aworld model), to generate real-time visualization simulations, for RADARsignal interpretation, for sound propagation synthesis and/or analysis,for simulation of SONAR systems, for general wave propagationsimulation, for comparison to LIDAR data for purposes of localizationand/or other functions, and/or for other uses.

In at least one embodiment, accelerator(s) 1014 can have a wide array ofuses for autonomous driving. In at least one embodiment, a PVA may beused for key processing stages in ADAS and autonomous vehicles. In atleast one embodiment, a PVA's capabilities are a good match foralgorithmic domains needing predictable processing, at low power and lowlatency. In other words, a PVA performs well on semi-dense or denseregular computation, even on small data sets, which might requirepredictable run-times with low latency and low power. In at least oneembodiment, such as in vehicle 1000, PVAs might be designed to runclassic computer vision algorithms, as they can be efficient at objectdetection and operating on integer math.

For example, according to at least one embodiment of technology, a PVAis used to perform computer stereo vision. In at least one embodiment, asemi-global matching-based algorithm may be used in some examples,although this is not intended to be limiting. In at least oneembodiment, applications for Level 3-5 autonomous driving use motionestimation/stereo matching on-the-fly (e.g., structure from motion,pedestrian recognition, lane detection, etc.). In at least oneembodiment, a PVA may perform computer stereo vision functions on inputsfrom two monocular cameras.

In at least one embodiment, a PVA may be used to perform dense opticalflow. For example, in at least one embodiment, a PVA could process rawRADAR data (e.g., using a 4D Fast Fourier Transform) to provideprocessed RADAR data. In at least one embodiment, a PVA is used for timeof flight depth processing, by processing raw time of flight data toprovide processed time of flight data, for example.

In at least one embodiment, a DLA may be used to run any type of networkto enhance control and driving safety, including for example and withoutlimitation, a neural network that outputs a measure of confidence foreach object detection. In at least one embodiment, confidence may berepresented or interpreted as a probability, or as providing a relative“weight” of each detection compared to other detections. In at least oneembodiment, a confidence measure enables a system to make furtherdecisions regarding which detections should be considered as truepositive detections rather than false positive detections. In at leastone embodiment, a system may set a threshold value for confidence andconsider only detections exceeding threshold value as true positivedetections. In an embodiment in which an automatic emergency braking(“AEB”) system is used, false positive detections would cause vehicle toautomatically perform emergency braking, which is obviously undesirable.In at least one embodiment, highly confident detections may beconsidered as triggers for AEB In at least one embodiment, a DLA may runa neural network for regressing confidence value. In at least oneembodiment, neural network may take as its input at least some subset ofparameters, such as bounding box dimensions, ground plane estimateobtained (e.g., from another subsystem), output from IMU sensor(s) 1066that correlates with vehicle 1000 orientation, distance, 3D locationestimates of object obtained from neural network and/or other sensors(e.g., LIDAR sensor(s) 1064 or RADAR sensor(s) 1060), among others.

In at least one embodiment, one or more of SoC(s) 1004 may include datastore(s) 1016 (e.g., memory). In at least one embodiment, data store(s)1016 may be on-chip memory of SoC(s) 1004, which may store neuralnetworks to be executed on GPU(s) 1008 and/or a DLA. In at least oneembodiment, data store(s) 1016 may be large enough in capacity to storemultiple instances of neural networks for redundancy and safety. In atleast one embodiment, data store(s) 1016 may comprise L2 or L3 cache(s).

In at least one embodiment, one or more of SoC(s) 1004 may include anynumber of processor(s) 1010 (e.g., embedded processors). In at least oneembodiment, processor(s) 1010 may include a boot and power managementprocessor that may be a dedicated processor and subsystem to handle bootpower and management functions and related security enforcement. In atleast one embodiment, a boot and power management processor may be apart of a boot sequence of SoC(s) 1004 and may provide runtime powermanagement services. In at least one embodiment, a boot power andmanagement processor may provide clock and voltage programming,assistance in system low power state transitions, management of SoC(s)1004 thermals and temperature sensors, and/or management of SoC(s) 1004power states. In at least one embodiment, each temperature sensor may beimplemented as a ring-oscillator whose output frequency is proportionalto temperature, and SoC(s) 1004 may use ring-oscillators to detecttemperatures of CPU(s) 1006, GPU(s) 1008, and/or accelerator(s) 1014. Inat least one embodiment, if temperatures are determined to exceed athreshold, then a boot and power management processor may enter atemperature fault routine and put SoC(s) 1004 into a lower power stateand/or put vehicle 1000 into a chauffeur to safe stop mode (e.g., bringvehicle 1000 to a safe stop).

In at least one embodiment, processor(s) 1010 may further include a setof embedded processors that may serve as an audio processing enginewhich may be an audio subsystem that enables full hardware support formulti-channel audio over multiple interfaces, and a broad and flexiblerange of audio I/O interfaces. In at least one embodiment, an audioprocessing engine is a dedicated processor core with a digital signalprocessor with dedicated RAM.

In at least one embodiment, processor(s) 1010 may further include analways-on processor engine that may provide necessary hardware featuresto support low power sensor management and wake use cases. In at leastone embodiment, an always-on processor engine may include, withoutlimitation, a processor core, a tightly coupled RAM, supportingperipherals (e.g., timers and interrupt controllers), various I/Ocontroller peripherals, and routing logic.

In at least one embodiment, processor(s) 1010 may further include asafety cluster engine that includes, without limitation, a dedicatedprocessor subsystem to handle safety management for automotiveapplications. In at least one embodiment, a safety cluster engine mayinclude, without limitation, two or more processor cores, a tightlycoupled RAM, support peripherals (e.g., timers, an interrupt controller,etc.), and/or routing logic. In a safety mode, two or more cores mayoperate, in at least one embodiment, in a lockstep mode and function asa single core with comparison logic to detect any differences betweentheir operations. In at least one embodiment, processor(s) 1010 mayfurther include a real-time camera engine that may include, withoutlimitation, a dedicated processor subsystem for handling real-timecamera management. In at least one embodiment, processor(s) 1010 mayfurther include a high-dynamic range signal processor that may include,without limitation, an image signal processor that is a hardware enginethat is part of a camera processing pipeline.

In at least one embodiment, processor(s) 1010 may include a video imagecompositor that may be a processing block (e.g., implemented on amicroprocessor) that implements video post-processing functions neededby a video playback application to produce a final image for a playerwindow. In at least one embodiment, a video image compositor may performlens distortion correction on wide-view camera(s) 1070, surroundcamera(s) 1074, and/or on in-cabin monitoring camera sensor(s). In atleast one embodiment, in-cabin monitoring camera sensor(s) are monitoredby a neural network running on another instance of SoC 1004, configuredto identify in cabin events and respond accordingly. In at least oneembodiment, an in-cabin system may perform, without limitation, lipreading to activate cellular service and place a phone call, dictateemails, change a vehicle's destination, activate or change a vehicle'sinfotainment system and settings, or provide voice-activated websurfing. In at least one embodiment, certain functions are available toa driver when a vehicle is operating in an autonomous mode and aredisabled otherwise.

In at least one embodiment, a video image compositor may includeenhanced temporal noise reduction for both spatial and temporal noisereduction. For example, in at least one embodiment, where motion occursin a video, noise reduction weights spatial information appropriately,decreasing weights of information provided by adjacent frames. In atleast one embodiment, where an image or portion of an image does notinclude motion, temporal noise reduction performed by video imagecompositor may use information from a previous image to reduce noise ina current image.

In at least one embodiment, a video image compositor may also beconfigured to perform stereo rectification on input stereo lens frames.In at least one embodiment, a video image compositor may further be usedfor user interface composition when an operating system desktop is inuse, and GPU(s) 1008 are not required to continuously render newsurfaces. In at least one embodiment, when GPU(s) 1008 are powered onand active doing 3D rendering, a video image compositor may be used tooffload GPU(s) 1008 to improve performance and responsiveness.

In at least one embodiment, one or more SoC of SoC(s) 1004 may furtherinclude a mobile industry processor interface (“MIPI”) camera serialinterface for receiving video and input from cameras, a high-speedinterface, and/or a video input block that may be used for a camera andrelated pixel input functions. In at least one embodiment, one or moreof SoC(s) 1004 may further include an input/output controller(s) thatmay be controlled by software and may be used for receiving I/O signalsthat are uncommitted to a specific role.

In at least one embodiment, one or more of SoC(s) 1004 may furtherinclude a broad range of peripheral interfaces to enable communicationwith peripherals, audio encoders/decoders (“codecs”), power management,and/or other devices. In at least one embodiment, SoC(s) 1004 may beused to process data from cameras (e.g., connected over GigabitMultimedia Serial Link and Ethernet channels), sensors (e.g., LIDARsensor(s) 1064, RADAR sensor(s) 1060, etc. that may be connected overEthernet channels), data from bus 1002 (e.g., speed of vehicle 1000,steering wheel position, etc.), data from GNSS sensor(s) 1058 (e.g.,connected over a Ethernet bus or a CAN bus), etc. In at least oneembodiment, one or more SoC of SoC(s) 1004 may further include dedicatedhigh-performance mass storage controllers that may include their own DMAengines, and that may be used to free CPU(s) 1006 from routine datamanagement tasks.

In at least one embodiment, SoC(s) 1004 may be an end-to-end platformwith a flexible architecture that spans automation Levels 3-5, therebyproviding a comprehensive functional safety architecture that leveragesand makes efficient use of computer vision and ADAS techniques fordiversity and redundancy, and provides a platform for a flexible,reliable driving software stack, along with deep learning tools. In atleast one embodiment, SoC(s) 1004 may be faster, more reliable, and evenmore energy-efficient and space-efficient than conventional systems. Forexample, in at least one embodiment, accelerator(s) 1014, when combinedwith CPU(s) 1006, GPU(s) 1008, and data store(s) 1016, may provide for afast, efficient platform for Level 3-5 autonomous vehicles.

In at least one embodiment, computer vision algorithms may be executedon CPUs, which may be configured using a high-level programminglanguage, such as C, to execute a wide variety of processing algorithmsacross a wide variety of visual data. However, in at least oneembodiment, CPUs are oftentimes unable to meet performance requirementsof many computer vision applications, such as those related to executiontime and power consumption, for example. In at least one embodiment,many CPUs are unable to execute complex object detection algorithms inreal-time, which is used in in-vehicle ADAS applications and inpractical Level 3-5 autonomous vehicles.

Embodiments described herein allow for multiple neural networks to beperformed simultaneously and/or sequentially, and for results to becombined together to enable Level 3-5 autonomous driving functionality.For example, in at least one embodiment, a CNN executing on a DLA or adiscrete GPU (e.g., GPU(s) 1020) may include text and word recognition,allowing reading and understanding of traffic signs, including signs forwhich a neural network has not been specifically trained. In at leastone embodiment, a DLA may further include a neural network that is ableto identify, interpret, and provide semantic understanding of a sign,and to pass that semantic understanding to path planning modules runningon a CPU Complex.

In at least one embodiment, multiple neural networks may be runsimultaneously, as for Level 3, 4, or 5 driving. For example, in atleast one embodiment, a warning sign stating “Caution: flashing lightsindicate icy conditions,” along with an electric light, may beindependently or collectively interpreted by several neural networks. Inat least one embodiment, such warning sign itself may be identified as atraffic sign by a first deployed neural network (e.g., a neural networkthat has been trained), text “flashing lights indicate icy conditions”may be interpreted by a second deployed neural network, which informs avehicle's path planning software (executing on a CPU Complex) that whenflashing lights are detected, icy conditions exist. In at least oneembodiment, a flashing light may be identified by operating a thirddeployed neural network over multiple frames, informing a vehicle'spath-planning software of a presence (or an absence) of flashing lights.In at least one embodiment, all three neural networks may runsimultaneously, such as within a DLA and/or on GPU(s) 1008.

In at least one embodiment, a CNN for facial recognition and vehicleowner identification may use data from camera sensors to identifypresence of an authorized driver and/or owner of vehicle 1000. In atleast one embodiment, an always-on sensor processing engine may be usedto unlock a vehicle when an owner approaches a driver door and turns onlights, and, in a security mode, to disable such vehicle when an ownerleaves such vehicle. In this way, SoC(s) 1004 provide for securityagainst theft and/or carj acking.

In at least one embodiment, a CNN for emergency vehicle detection andidentification may use data from microphones 1096 to detect and identifyemergency vehicle sirens. In at least one embodiment, SoC(s) 1004 use aCNN for classifying environmental and urban sounds, as well asclassifying visual data. In at least one embodiment, a CNN running on aDLA is trained to identify a relative closing speed of an emergencyvehicle (e.g., by using a Doppler effect). In at least one embodiment, aCNN may also be trained to identify emergency vehicles specific to alocal area in which a vehicle is operating, as identified by GNSSsensor(s) 1058. In at least one embodiment, when operating in Europe, aCNN will seek to detect European sirens, and when in North America, aCNN will seek to identify only North American sirens. In at least oneembodiment, once an emergency vehicle is detected, a control program maybe used to execute an emergency vehicle safety routine, slowing avehicle, pulling over to a side of a road, parking a vehicle, and/oridling a vehicle, with assistance of ultrasonic sensor(s) 1062, untilemergency vehicles pass.

In at least one embodiment, vehicle 1000 may include CPU(s) 1018 (e.g.,discrete CPU(s), or dCPU(s)), that may be coupled to SoC(s) 1004 via ahigh-speed interconnect (e.g., PCIe). In at least one embodiment, CPU(s)1018 may include an X86 processor, for example. CPU(s) 1018 may be usedto perform any of a variety of functions, including arbitratingpotentially inconsistent results between ADAS sensors and SoC(s) 1004,and/or monitoring status and health of controller(s) 1036 and/or aninfotainment system on a chip (“infotainment SoC”) 1030, for example.

In at least one embodiment, vehicle 1000 may include GPU(s) 1020 (e.g.,discrete GPU(s), or dGPU(s)), that may be coupled to SoC(s) 1004 via ahigh-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least oneembodiment, GPU(s) 1020 may provide additional artificial intelligencefunctionality, such as by executing redundant and/or different neuralnetworks, and may be used to train and/or update neural networks basedat least in part on input (e.g., sensor data) from sensors of a vehicle1000.

In at least one embodiment, vehicle 1000 may further include networkinterface 1024 which may include, without limitation, wirelessantenna(s) 1026 (e.g., one or more wireless antennas for differentcommunication protocols, such as a cellular antenna, a Bluetoothantenna, etc.). In at least one embodiment, network interface 1024 maybe used to enable wireless connectivity to Internet cloud services(e.g., with server(s) and/or other network devices), with othervehicles, and/or with computing devices (e.g., client devices ofpassengers). In at least one embodiment, to communicate with othervehicles, a direct link may be established between vehicle 1000 andanother vehicle and/or an indirect link may be established (e.g., acrossnetworks and over the Internet). In at least one embodiment, directlinks may be provided using a vehicle-to-vehicle communication link. Inat least one embodiment, a vehicle-to-vehicle communication link mayprovide vehicle 1000 information about vehicles in proximity to vehicle1000 (e.g., vehicles in front of, on a side of, and/or behind vehicle1000). In at least one embodiment, such aforementioned functionality maybe part of a cooperative adaptive cruise control functionality ofvehicle 1000.

In at least one embodiment, network interface 1024 may include an SoCthat provides modulation and demodulation functionality and enablescontroller(s) 1036 to communicate over wireless networks. In at leastone embodiment, network interface 1024 may include a radio frequencyfront-end for up-conversion from baseband to radio frequency, and downconversion from radio frequency to baseband. In at least one embodiment,frequency conversions may be performed in any technically feasiblefashion. For example, frequency conversions could be performed throughwell-known processes, and/or using super-heterodyne processes. In atleast one embodiment, radio frequency front end functionality may beprovided by a separate chip. In at least one embodiment, networkinterfaces may include wireless functionality for communicating overLTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave,ZigBee, LoRaWAN, and/or other wireless protocols.

In at least one embodiment, vehicle 1000 may further include datastore(s) 1028 which may include, without limitation, off-chip (e.g., offSoC(s) 1004) storage. In at least one embodiment, data store(s) 1028 mayinclude, without limitation, one or more storage elements including RAM,SRAM, dynamic random-access memory (“DRAM”), video random-access memory(“VRAM”), flash memory, hard disks, and/or other components and/ordevices that may store at least one bit of data.

In at least one embodiment, vehicle 1000 may further include GNSSsensor(s) 1058 (e.g., GPS and/or assisted GPS sensors), to assist inmapping, perception, occupancy grid generation, and/or path planningfunctions. In at least one embodiment, any number of GNSS sensor(s) 1058may be used, including, for example and without limitation, a GPS usinga Universal Serial Bus (“USB”) connector with an Ethernet-to-Serial(e.g., RS-232) bridge.

In at least one embodiment, vehicle 1000 may further include RADARsensor(s) 1060. In at least one embodiment, RADAR sensor(s) 1060 may beused by vehicle 1000 for long-range vehicle detection, even in darknessand/or severe weather conditions. In at least one embodiment, RADARfunctional safety levels may be ASIL B. In at least one embodiment,RADAR sensor(s) 1060 may use a CAN bus and/or bus 1002 (e.g., totransmit data generated by RADAR sensor(s) 1060) for control and toaccess object tracking data, with access to Ethernet channels to accessraw data in some examples. In at least one embodiment, a wide variety ofRADAR sensor types may be used. For example, and without limitation,RADAR sensor(s) 1060 may be suitable for front, rear, and side RADARuse. In at least one embodiment, one or more sensor of RADAR sensors(s)1060 is a Pulse Doppler RADAR sensor.

In at least one embodiment, RADAR sensor(s) 1060 may include differentconfigurations, such as long-range with narrow field of view,short-range with wide field of view, short-range side coverage, etc. Inat least one embodiment, long-range RADAR may be used for adaptivecruise control functionality. In at least one embodiment, long-rangeRADAR systems may provide a broad field of view realized by two or moreindependent scans, such as within a 250 m (meter) range. In at least oneembodiment, RADAR sensor(s) 1060 may help in distinguishing betweenstatic and moving objects, and may be used by ADAS system 1038 foremergency brake assist and forward collision warning. In at least oneembodiment, sensors 1060(s) included in a long-range RADAR system mayinclude, without limitation, monostatic multimodal RADAR with multiple(e.g., six or more) fixed RADAR antennae and a high-speed CAN andFlexRay interface. In at least one embodiment, with six antennae, acentral four antennae may create a focused beam pattern, designed torecord vehicle's 1000 surroundings at higher speeds with minimalinterference from traffic in adjacent lanes. In at least one embodiment,another two antennae may expand field of view, making it possible toquickly detect vehicles entering or leaving a lane of vehicle 1000.

In at least one embodiment, mid-range RADAR systems may include, as anexample, a range of up to 160 m (front) or 80 m (rear), and a field ofview of up to 42 degrees (front) or 150 degrees (rear). In at least oneembodiment, short-range RADAR systems may include, without limitation,any number of RADAR sensor(s) 1060 designed to be installed at both endsof a rear bumper. When installed at both ends of a rear bumper, in atleast one embodiment, a RADAR sensor system may create two beams thatconstantly monitor blind spots in a rear direction and next to avehicle. In at least one embodiment, short-range RADAR systems may beused in ADAS system 1038 for blind spot detection and/or lane changeassist.

In at least one embodiment, vehicle 1000 may further include ultrasonicsensor(s) 1062. In at least one embodiment, ultrasonic sensor(s) 1062,which may be positioned at a front, a back, and/or side location ofvehicle 1000, may be used for parking assist and/or to create and updatean occupancy grid. In at least one embodiment, a wide variety ofultrasonic sensor(s) 1062 may be used, and different ultrasonicsensor(s) 1062 may be used for different ranges of detection (e.g., 2.5m, 4 m). In at least one embodiment, ultrasonic sensor(s) 1062 mayoperate at functional safety levels of ASIL B.

In at least one embodiment, vehicle 1000 may include LIDAR sensor(s)1064. In at least one embodiment, LIDAR sensor(s) 1064 may be used forobject and pedestrian detection, emergency braking, collision avoidance,and/or other functions. In at least one embodiment, LIDAR sensor(s) 1064may operate at functional safety level ASIL B. In at least oneembodiment, vehicle 1000 may include multiple LIDAR sensors 1064 (e.g.,two, four, six, etc.) that may use an Ethernet channel (e.g., to providedata to a Gigabit Ethernet switch).

In at least one embodiment, LIDAR sensor(s) 1064 may be capable ofproviding a list of objects and their distances for a 360-degree fieldof view. In at least one embodiment, commercially available LIDARsensor(s) 1064 may have an advertised range of approximately 100 m, withan accuracy of 2 cm to 3 cm, and with support for a 100 Mbps Ethernetconnection, for example. In at least one embodiment, one or morenon-protruding LIDAR sensors may be used. In such an embodiment, LIDARsensor(s) 1064 may include a small device that may be embedded into afront, a rear, a side, and/or a corner location of vehicle 1000. In atleast one embodiment, LIDAR sensor(s) 1064, in such an embodiment, mayprovide up to a 120-degree horizontal and 35-degree verticalfield-of-view, with a 200 m range even for low-reflectivity objects. Inat least one embodiment, front-mounted LIDAR sensor(s) 1064 may beconfigured for a horizontal field of view between 45 degrees and 135degrees.

In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR,may also be used. In at least one embodiment, 3D flash LIDAR uses aflash of a laser as a transmission source, to illuminate surroundings ofvehicle 1000 up to approximately 200 m. In at least one embodiment, aflash LIDAR unit includes, without limitation, a receptor, which recordslaser pulse transit time and reflected light on each pixel, which inturn corresponds to a range from vehicle 1000 to objects. In at leastone embodiment, flash LIDAR may allow for highly accurate anddistortion-free images of surroundings to be generated with every laserflash. In at least one embodiment, four flash LIDAR sensors may bedeployed, one at each side of vehicle 1000. In at least one embodiment,3D flash LIDAR systems include, without limitation, a solid-state 3Dstaring array LIDAR camera with no moving parts other than a fan (e.g.,a non-scanning LIDAR device). In at least one embodiment, flash LIDARdevice may use a 5 nanosecond class I (eye-safe) laser pulse per frameand may capture reflected laser light as a 3D range point cloud andco-registered intensity data.

In at least one embodiment, vehicle 1000 may further include IMUsensor(s) 1066. In at least one embodiment, IMU sensor(s) 1066 may belocated at a center of a rear axle of vehicle 1000. In at least oneembodiment, IMU sensor(s) 1066 may include, for example and withoutlimitation, accelerometer(s), magnetometer(s), gyroscope(s), a magneticcompass, magnetic compasses, and/or other sensor types. In at least oneembodiment, such as in six-axis applications, IMU sensor(s) 1066 mayinclude, without limitation, accelerometers and gyroscopes. In at leastone embodiment, such as in nine-axis applications, IMU sensor(s) 1066may include, without limitation, accelerometers, gyroscopes, andmagnetometers.

In at least one embodiment, IMU sensor(s) 1066 may be implemented as aminiature, high performance GPS-Aided Inertial Navigation System(“GPS/INS”) that combines micro-electro-mechanical systems (“MEMS”)inertial sensors, a high-sensitivity GPS receiver, and advanced Kalmanfiltering algorithms to provide estimates of position, velocity, andattitude. In at least one embodiment, IMU sensor(s) 1066 may enablevehicle 1000 to estimate its heading without requiring input from amagnetic sensor by directly observing and correlating changes invelocity from a GPS to IMU sensor(s) 1066. In at least one embodiment,IMU sensor(s) 1066 and GNSS sensor(s) 1058 may be combined in a singleintegrated unit.

In at least one embodiment, vehicle 1000 may include microphone(s) 1096placed in and/or around vehicle 1000. In at least one embodiment,microphone(s) 1096 may be used for emergency vehicle detection andidentification, among other things.

In at least one embodiment, vehicle 1000 may further include any numberof camera types, including stereo camera(s) 1068, wide-view camera(s)1070, infrared camera(s) 1072, surround camera(s) 1074, long-rangecamera(s) 1098, mid-range camera(s) 1076, and/or other camera types. Inat least one embodiment, cameras may be used to capture image dataaround an entire periphery of vehicle 1000. In at least one embodiment,which types of cameras used depends on vehicle 1000. In at least oneembodiment, any combination of camera types may be used to providenecessary coverage around vehicle 1000. In at least one embodiment, anumber of cameras deployed may differ depending on embodiment. Forexample, in at least one embodiment, vehicle 1000 could include sixcameras, seven cameras, ten cameras, twelve cameras, or another numberof cameras. In at least one embodiment, cameras may support, as anexample and without limitation, Gigabit Multimedia Serial Link (“GMSL”)and/or Gigabit Ethernet communications. In at least one embodiment, eachcamera might be as described with more detail previously herein withrespect to FIG. 10A and FIG. 10B.

In at least one embodiment, vehicle 1000 may further include vibrationsensor(s) 1042. In at least one embodiment, vibration sensor(s) 1042 maymeasure vibrations of components of vehicle 1000, such as axle(s). Forexample, in at least one embodiment, changes in vibrations may indicatea change in road surfaces. In at least one embodiment, when two or morevibration sensors 1042 are used, differences between vibrations may beused to determine friction or slippage of road surface (e.g., when adifference in vibration is between a power-driven axle and a freelyrotating axle).

In at least one embodiment, vehicle 1000 may include ADAS system 1038.In at least one embodiment, ADAS system 1038 may include, withoutlimitation, an SoC, in some examples. In at least one embodiment, ADASsystem 1038 may include, without limitation, any number and combinationof an autonomous/adaptive/automatic cruise control (“ACC”) system, acooperative adaptive cruise control (“CACC”) system, a forward crashwarning (“FCW”) system, an automatic emergency braking (“AEB”) system, alane departure warning (“LDW)” system, a lane keep assist (“LKA”)system, a blind spot warning (“BSW”) system, a rear cross-trafficwarning (“RCTW”) system, a collision warning (“CW”) system, a lanecentering (“LC”) system, and/or other systems, features, and/orfunctionality.

In at least one embodiment, ACC system may use RADAR sensor(s) 1060,LIDAR sensor(s) 1064, and/or any number of camera(s). In at least oneembodiment, ACC system may include a longitudinal ACC system and/or alateral ACC system. In at least one embodiment, a longitudinal ACCsystem monitors and controls distance to another vehicle immediatelyahead of vehicle 1000 and automatically adjusts speed of vehicle 1000 tomaintain a safe distance from vehicles ahead. In at least oneembodiment, a lateral ACC system performs distance keeping, and advisesvehicle 1000 to change lanes when necessary. In at least one embodiment,a lateral ACC is related to other ADAS applications, such as LC and CW.

In at least one embodiment, a CACC system uses information from othervehicles that may be received via network interface 1024 and/or wirelessantenna(s) 1026 from other vehicles via a wireless link, or indirectly,over a network connection (e.g., over the Internet). In at least oneembodiment, direct links may be provided by a vehicle-to-vehicle (“V2V”)communication link, while indirect links may be provided by aninfrastructure-to-vehicle (“I2V”) communication link. In general, V2Vcommunication provides information about immediately preceding vehicles(e.g., vehicles immediately ahead of and in same lane as vehicle 1000),while I2V communication provides information about traffic furtherahead. In at least one embodiment, a CACC system may include either orboth I2V and V2V information sources. In at least one embodiment, giveninformation of vehicles ahead of vehicle 1000, a CACC system may be morereliable and it has potential to improve traffic flow smoothness andreduce congestion on road.

In at least one embodiment, an FCW system is designed to alert a driverto a hazard, so that such driver may take corrective action. In at leastone embodiment, an FCW system uses a front-facing camera and/or RADARsensor(s) 1060, coupled to a dedicated processor, digital signalprocessor (“DSP”), FPGA, and/or ASIC, that is electrically coupled toprovide driver feedback, such as a display, speaker, and/or vibratingcomponent. In at least one embodiment, an FCW system may provide awarning, such as in form of a sound, visual warning, vibration and/or aquick brake pulse.

In at least one embodiment, an AEB system detects an impending forwardcollision with another vehicle or other object, and may automaticallyapply brakes if a driver does not take corrective action within aspecified time or distance parameter. In at least one embodiment, AEBsystem may use front-facing camera(s) and/or RADAR sensor(s) 1060,coupled to a dedicated processor, DSP, FPGA, and/or ASIC. In at leastone embodiment, when an AEB system detects a hazard, it will typicallyfirst alert a driver to take corrective action to avoid collision and,if that driver does not take corrective action, that AEB system mayautomatically apply brakes in an effort to prevent, or at leastmitigate, an impact of a predicted collision. In at least oneembodiment, an AEB system may include techniques such as dynamic brakesupport and/or crash imminent braking.

In at least one embodiment, an LDW system provides visual, audible,and/or tactile warnings, such as steering wheel or seat vibrations, toalert driver when vehicle 1000 crosses lane markings. In at least oneembodiment, an LDW system does not activate when a driver indicates anintentional lane departure, such as by activating a turn signal. In atleast one embodiment, an LDW system may use front-side facing cameras,coupled to a dedicated processor, DSP, FPGA, and/or ASIC, that iselectrically coupled to provide driver feedback, such as a display,speaker, and/or vibrating component. In at least one embodiment, an LKAsystem is a variation of an LDW system. In at least one embodiment, anLKA system provides steering input or braking to correct vehicle 1000 ifvehicle 1000 starts to exit its lane.

In at least one embodiment, a BSW system detects and warns a driver ofvehicles in an automobile's blind spot. In at least one embodiment, aBSW system may provide a visual, audible, and/or tactile alert toindicate that merging or changing lanes is unsafe. In at least oneembodiment, a BSW system may provide an additional warning when a driveruses a turn signal. In at least one embodiment, a BSW system may userear-side facing camera(s) and/or RADAR sensor(s) 1060, coupled to adedicated processor, DSP, FPGA, and/or ASIC, that is electricallycoupled to driver feedback, such as a display, speaker, and/or vibratingcomponent.

In at least one embodiment, an RCTW system may provide visual, audible,and/or tactile notification when an object is detected outside arear-camera range when vehicle 1000 is backing up. In at least oneembodiment, an RCTW system includes an AEB system to ensure that vehiclebrakes are applied to avoid a crash. In at least one embodiment, an RCTWsystem may use one or more rear-facing RADAR sensor(s) 1060, coupled toa dedicated processor, DSP, FPGA, and/or ASIC, that is electricallycoupled to provide driver feedback, such as a display, speaker, and/orvibrating component.

In at least one embodiment, conventional ADAS systems may be prone tofalse positive results which may be annoying and distracting to adriver, but typically are not catastrophic, because conventional ADASsystems alert a driver and allow that driver to decide whether a safetycondition truly exists and act accordingly. In at least one embodiment,vehicle 1000 itself decides, in case of conflicting results, whether toheed result from a primary computer or a secondary computer (e.g., afirst controller or a second controller of controllers 1036). Forexample, in at least one embodiment, ADAS system 1038 may be a backupand/or secondary computer for providing perception information to abackup computer rationality module. In at least one embodiment, a backupcomputer rationality monitor may run redundant diverse software onhardware components to detect faults in perception and dynamic drivingtasks. In at least one embodiment, outputs from ADAS system 1038 may beprovided to a supervisory MCU. In at least one embodiment, if outputsfrom a primary computer and outputs from a secondary computer conflict,a supervisory MCU determines how to reconcile conflict to ensure safeoperation.

In at least one embodiment, a primary computer may be configured toprovide a supervisory MCU with a confidence score, indicating thatprimary computer's confidence in a chosen result. In at least oneembodiment, if that confidence score exceeds a threshold, thatsupervisory MCU may follow that primary computer's direction, regardlessof whether that secondary computer provides a conflicting orinconsistent result. In at least one embodiment, where a confidencescore does not meet a threshold, and where primary and secondarycomputers indicate different results (e.g., a conflict), a supervisoryMCU may arbitrate between computers to determine an appropriate outcome.

In at least one embodiment, a supervisory MCU may be configured to run aneural network(s) that is trained and configured to determine, based atleast in part on outputs from a primary computer and outputs from asecondary computer, conditions under which that secondary computerprovides false alarms. In at least one embodiment, neural network(s) ina supervisory MCU may learn when a secondary computer's output may betrusted, and when it cannot. For example, in at least one embodiment,when that secondary computer is a RADAR-based FCW system, a neuralnetwork(s) in that supervisory MCU may learn when an FCW system isidentifying metallic objects that are not, in fact, hazards, such as adrainage grate or manhole cover that triggers an alarm. In at least oneembodiment, when a secondary computer is a camera-based LDW system, aneural network in a supervisory MCU may learn to override LDW whenbicyclists or pedestrians are present and a lane departure is, in fact,a safest maneuver. In at least one embodiment, a supervisory MCU mayinclude at least one of a DLA or a GPU suitable for running neuralnetwork(s) with associated memory. In at least one embodiment, asupervisory MCU may comprise and/or be included as a component of SoC(s)1004.

In at least one embodiment, ADAS system 1038 may include a secondarycomputer that performs ADAS functionality using traditional rules ofcomputer vision. In at least one embodiment, that secondary computer mayuse classic computer vision rules (if-then), and presence of a neuralnetwork(s) in a supervisory MCU may improve reliability, safety andperformance. For example, in at least one embodiment, diverseimplementation and intentional non-identity makes an overall system morefault-tolerant, especially to faults caused by software (orsoftware-hardware interface) functionality. For example, in at least oneembodiment, if there is a software bug or error in software running on aprimary computer, and non-identical software code running on a secondarycomputer provides a consistent overall result, then a supervisory MCUmay have greater confidence that an overall result is correct, and a bugin software or hardware on that primary computer is not causing amaterial error.

In at least one embodiment, an output of ADAS system 1038 may be fedinto a primary computer's perception block and/or a primary computer'sdynamic driving task block. For example, in at least one embodiment, ifADAS system 1038 indicates a forward crash warning due to an objectimmediately ahead, a perception block may use this information whenidentifying objects. In at least one embodiment, a secondary computermay have its own neural network that is trained and thus reduces a riskof false positives, as described herein.

In at least one embodiment, vehicle 1000 may further includeinfotainment SoC 1030 (e.g., an in-vehicle infotainment system (IVI)).Although illustrated and described as an SoC, infotainment system SoC1030, in at least one embodiment, may not be an SoC, and may include,without limitation, two or more discrete components. In at least oneembodiment, infotainment SoC 1030 may include, without limitation, acombination of hardware and software that may be used to provide audio(e.g., music, a personal digital assistant, navigational instructions,news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone(e.g., hands-free calling), network connectivity (e.g., LTE, WiFi,etc.), and/or information services (e.g., navigation systems,rear-parking assistance, a radio data system, vehicle relatedinformation such as fuel level, total distance covered, brake fuellevel, oil level, door open/close, air filter information, etc.) tovehicle 1000. For example, infotainment SoC 1030 could include radios,disk players, navigation systems, video players, USB and Bluetoothconnectivity, carputers, in-car entertainment, WiFi, steering wheelaudio controls, hands free voice control, a heads-up display (“HUD”),HMI display 1034, a telematics device, a control panel (e.g., forcontrolling and/or interacting with various components, features, and/orsystems), and/or other components. In at least one embodiment,infotainment SoC 1030 may further be used to provide information (e.g.,visual and/or audible) to user(s) of vehicle 1000, such as informationfrom ADAS system 1038, autonomous driving information such as plannedvehicle maneuvers, trajectories, surrounding environment information(e.g., intersection information, vehicle information, road information,etc.), and/or other information.

In at least one embodiment, infotainment SoC 1030 may include any amountand type of GPU functionality. In at least one embodiment, infotainmentSoC 1030 may communicate over bus 1002 with other devices, systems,and/or components of vehicle 1000. In at least one embodiment,infotainment SoC 1030 may be coupled to a supervisory MCU such that aGPU of an infotainment system may perform some self-driving functions inevent that primary controller(s) 1036 (e.g., primary and/or backupcomputers of vehicle 1000) fail. In at least one embodiment,infotainment SoC 1030 may put vehicle 1000 into a chauffeur to safe stopmode, as described herein.

In at least one embodiment, vehicle 1000 may further include instrumentcluster 1032 (e.g., a digital dash, an electronic instrument cluster, adigital instrument panel, etc.). In at least one embodiment, instrumentcluster 1032 may include, without limitation, a controller and/orsupercomputer (e.g., a discrete controller or supercomputer). In atleast one embodiment, instrument cluster 1032 may include, withoutlimitation, any number and combination of a set of instrumentation suchas a speedometer, fuel level, oil pressure, tachometer, odometer, turnindicators, gearshift position indicator, seat belt warning light(s),parking-brake warning light(s), engine-malfunction light(s),supplemental restraint system (e.g., airbag) information, lightingcontrols, safety system controls, navigation information, etc. In someexamples, information may be displayed and/or shared among infotainmentSoC 1030 and instrument cluster 1032. In at least one embodiment,instrument cluster 1032 may be included as part of infotainment SoC1030, or vice versa.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used in systemFIG. 10C for inferencing or predicting operations based, at least inpart, on weight parameters calculated using neural network trainingoperations, neural network functions and/or architectures, or neuralnetwork use cases described herein.

FIG. 10D is a diagram of a system 1079 for communication betweencloud-based server(s) and autonomous vehicle 1000 of FIG. 10A, accordingto at least one embodiment. In at least one embodiment, system 1079 mayinclude, without limitation, server(s) 1078, network(s) 1090, and anynumber and type of vehicles, including vehicle 1000. In at least oneembodiment, server(s) 1078 may include, without limitation, a pluralityof GPUs 1084(A)-1084(H) (collectively referred to herein as GPUs 1084),PCIe switches 1082(A)-1082(D) (collectively referred to herein as PCIeswitches 1082), and/or CPUs 1080(A)-1080(B) (collectively referred toherein as CPUs 1080). In at least one embodiment, GPUs 1084, CPUs 1080,and PCIe switches 1082 may be interconnected with high-speedinterconnects such as, for example and without limitation, NVLinkinterfaces 1088 developed by NVIDIA and/or PCIe connections 1086. In atleast one embodiment, GPUs 1084 are connected via an NVLink and/orNVSwitch SoC and GPUs 1084 and PCIe switches 1082 are connected via PCIeinterconnects. Although eight GPUs 1084, two CPUs 1080, and four PCIeswitches 1082 are illustrated, this is not intended to be limiting. Inat least one embodiment, each of server(s) 1078 may include, withoutlimitation, any number of GPUs 1084, CPUs 1080, and/or PCIe switches1082, in any combination. For example, in at least one embodiment,server(s) 1078 could each include eight, sixteen, thirty-two, and/ormore GPUs 1084.

In at least one embodiment, server(s) 1078 may receive, over network(s)1090 and from vehicles, image data representative of images showingunexpected or changed road conditions, such as recently commencedroad-work. In at least one embodiment, server(s) 1078 may transmit, overnetwork(s) 1090 and to vehicles, neural networks 1092, updated orotherwise, and/or map information 1094, including, without limitation,information regarding traffic and road conditions. In at least oneembodiment, updates to map information 1094 may include, withoutlimitation, updates for HD map 1022, such as information regardingconstruction sites, potholes, detours, flooding, and/or otherobstructions. In at least one embodiment, neural networks 1092, and/ormap information 1094 may have resulted from new training and/orexperiences represented in data received from any number of vehicles inan environment, and/or based at least in part on training performed at adata center (e.g., using server(s) 1078 and/or other servers).

In at least one embodiment, server(s) 1078 may be used to train machinelearning models (e.g., neural networks) based at least in part ontraining data. In at least one embodiment, training data may begenerated by vehicles, and/or may be generated in a simulation (e.g.,using a game engine). In at least one embodiment, any amount of trainingdata is tagged (e.g., where associated neural network benefits fromsupervised learning) and/or undergoes other pre-processing. In at leastone embodiment, any amount of training data is not tagged and/orpre-processed (e.g., where associated neural network does not requiresupervised learning). In at least one embodiment, once machine learningmodels are trained, machine learning models may be used by vehicles(e.g., transmitted to vehicles over network(s) 1090), and/or machinelearning models may be used by server(s) 1078 to remotely monitorvehicles.

In at least one embodiment, server(s) 1078 may receive data fromvehicles and apply data to up-to-date real-time neural networks forreal-time intelligent inferencing. In at least one embodiment, server(s)1078 may include deep-learning supercomputers and/or dedicated AIcomputers powered by GPU(s) 1084, such as a DGX and DGX Station machinesdeveloped by NVIDIA. However, in at least one embodiment, server(s) 1078may include deep learning infrastructure that uses CPU-powered datacenters.

In at least one embodiment, deep-learning infrastructure of server(s)1078 may be capable of fast, real-time inferencing, and may use thatcapability to evaluate and verify health of processors, software, and/orassociated hardware in vehicle 1000. For example, in at least oneembodiment, deep-learning infrastructure may receive periodic updatesfrom vehicle 1000, such as a sequence of images and/or objects thatvehicle 1000 has located in that sequence of images (e.g., via computervision and/or other machine learning object classification techniques).In at least one embodiment, deep-learning infrastructure may run its ownneural network to identify objects and compare them with objectsidentified by vehicle 1000 and, if results do not match anddeep-learning infrastructure concludes that AI in vehicle 1000 ismalfunctioning, then server(s) 1078 may transmit a signal to vehicle1000 instructing a fail-safe computer of vehicle 1000 to assume control,notify passengers, and complete a safe parking maneuver.

In at least one embodiment, server(s) 1078 may include GPU(s) 1084 andone or more programmable inference accelerators (e.g., NVIDIA's TensorRT3 devices). In at least one embodiment, a combination of GPU-poweredservers and inference acceleration may make real-time responsivenesspossible. In at least one embodiment, such as where performance is lesscritical, servers powered by CPUs, FPGAs, and other processors may beused for inferencing. In at least one embodiment, hardware structure(s)115 are used to perform one or more embodiments. Details regardinghardware structure(x) 115 are provided herein in conjunction with FIGS.1A and/or 1B.

Computer Systems

FIG. 11 is a block diagram illustrating an exemplary computer system,which may be a system with interconnected devices and components, asystem-on-a-chip (SOC) or some combination thereof formed with aprocessor that may include execution units to execute an instruction,according to at least one embodiment. In at least one embodiment, acomputer system 1100 may include, without limitation, a component, suchas a processor 1102 to employ execution units including logic to performalgorithms for process data, in accordance with present disclosure, suchas in embodiment described herein. In at least one embodiment, computersystem 1100 may include processors, such as PENTIUM® Processor family,Xeon™ Itanium®, XScale™ and/or StrongARM™, Intel® Core™, or Intel®Nervana™ microprocessors available from Intel Corporation of SantaClara, Calif., although other systems (including PCs having othermicroprocessors, engineering workstations, set-top boxes and like) mayalso be used. In at least one embodiment, computer system 1100 mayexecute a version of WINDOWS operating system available from MicrosoftCorporation of Redmond, Wash., although other operating systems (UNIXand Linux, for example), embedded software, and/or graphical userinterfaces, may also be used.

Embodiments may be used in other devices such as handheld devices andembedded applications. Some examples of handheld devices includecellular phones, Internet Protocol devices, digital cameras, personaldigital assistants (“PDAs”), and handheld PCs. In at least oneembodiment, embedded applications may include a microcontroller, a DSP,system on a chip, network computers (“NetPCs”), set-top boxes, networkhubs, wide area network (“WAN”) switches, or any other system that mayperform one or more instructions in accordance with at least oneembodiment.

In at least one embodiment, computer system 1100 may include, withoutlimitation, processor 1102 that may include, without limitation, one ormore execution units 1108 to perform machine learning model trainingand/or inferencing according to techniques described herein. In at leastone embodiment, computer system 1100 is a single processor desktop orserver system, but in at least one other embodiment, computer system1100 may be a multiprocessor system. In at least one embodiment,processor 1102 may include, without limitation, a complex instructionset computer (“CISC”) microprocessor, a reduced instruction setcomputing (“RISC”) microprocessor, a very long instruction word (“VLIW”)microprocessor, a processor implementing a combination of instructionsets, or any other processor device, such as a digital signal processor,for example. In at least one embodiment, processor 1102 may be coupledto a processor bus 1110 that may transmit data signals between processor1102 and other components in computer system 1100.

In at least one embodiment, processor 1102 may include, withoutlimitation, a Level 1 (“L1”) internal cache memory (“cache”) 1104. In atleast one embodiment, processor 1102 may have a single internal cache ormultiple levels of internal cache. In at least one embodiment, cachememory may reside external to processor 1102. Other embodiments may alsoinclude a combination of both internal and external caches depending onparticular implementation and needs. In at least one embodiment, aregister file 1106 may store different types of data in variousregisters including, without limitation, integer registers, floatingpoint registers, status registers, and an instruction pointer register.

In at least one embodiment, execution unit 1108, including, withoutlimitation, logic to perform integer and floating point operations, alsoresides in processor 1102. In at least one embodiment, processor 1102may also include a microcode (“ucode”) read only memory (“ROM”) thatstores microcode for certain macro instructions. In at least oneembodiment, execution unit 1108 may include logic to handle a packedinstruction set 1109. In at least one embodiment, by including packedinstruction set 1109 in an instruction set of a general-purposeprocessor, along with associated circuitry to execute instructions,operations used by many multimedia applications may be performed usingpacked data in processor 1102. In at least one embodiment, manymultimedia applications may be accelerated and executed more efficientlyby using a full width of a processor's data bus for performingoperations on packed data, which may eliminate a need to transfersmaller units of data across that processor's data bus to perform one ormore operations one data element at a time.

In at least one embodiment, execution unit 1108 may also be used inmicrocontrollers, embedded processors, graphics devices, DSPs, and othertypes of logic circuits. In at least one embodiment, computer system1100 may include, without limitation, a memory 1120. In at least oneembodiment, memory 1120 may be a Dynamic Random Access Memory (“DRAM”)device, a Static Random Access Memory (“SRAM”) device, a flash memorydevice, or another memory device. In at least one embodiment, memory1120 may store instruction(s) 1119 and/or data 1121 represented by datasignals that may be executed by processor 1102.

In at least one embodiment, a system logic chip may be coupled toprocessor bus 1110 and memory 1120. In at least one embodiment, a systemlogic chip may include, without limitation, a memory controller hub(“MCH”) 1116, and processor 1102 may communicate with MCH 1116 viaprocessor bus 1110. In at least one embodiment, MCH 1116 may provide ahigh bandwidth memory path 1118 to memory 1120 for instruction and datastorage and for storage of graphics commands, data and textures. In atleast one embodiment, MCH 1116 may direct data signals between processor1102, memory 1120, and other components in computer system 1100 and tobridge data signals between processor bus 1110, memory 1120, and asystem I/O interface 1122. In at least one embodiment, a system logicchip may provide a graphics port for coupling to a graphics controller.In at least one embodiment, MCH 1116 may be coupled to memory 1120through high bandwidth memory path 1118 and a graphics/video card 1112may be coupled to MCH 1116 through an Accelerated Graphics Port (“AGP”)interconnect 1114.

In at least one embodiment, computer system 1100 may use system I/Ointerface 1122 as a proprietary hub interface bus to couple MCH 1116 toan I/O controller hub (“ICH”) 1130. In at least one embodiment, ICH 1130may provide direct connections to some I/O devices via a local I/O bus.In at least one embodiment, a local I/O bus may include, withoutlimitation, a high-speed I/O bus for connecting peripherals to memory1120, a chipset, and processor 1102. Examples may include, withoutlimitation, an audio controller 1129, a firmware hub (“flash BIOS”)1128, a wireless transceiver 1126, a data storage 1124, a legacy I/Ocontroller 1123 containing user input and keyboard interfaces 1125, aserial expansion port 1127, such as a USB port, and a network controller1134. In at least one embodiment, data storage 1124 may comprise a harddisk drive, a floppy disk drive, a CD-ROM device, a flash memory device,or other mass storage device.

In at least one embodiment, FIG. 11 illustrates a system, which includesinterconnected hardware devices or “chips”, whereas in otherembodiments, FIG. 11 may illustrate an exemplary SoC. In at least oneembodiment, devices illustrated in FIG. 11 may be interconnected withproprietary interconnects, standardized interconnects (e.g., PCIe) orsome combination thereof. In at least one embodiment, one or morecomponents of computer system 1100 are interconnected using computeexpress link (CXL) interconnects.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used in systemFIG. 11 for inferencing or predicting operations based, at least inpart, on weight parameters calculated using neural network trainingoperations, neural network functions and/or architectures, or neuralnetwork use cases described herein.

FIG. 12 is a block diagram illustrating an electronic device 1200 forutilizing a processor 1210, according to at least one embodiment. In atleast one embodiment, electronic device 1200 may be, for example andwithout limitation, a notebook, a tower server, a rack server, a bladeserver, a laptop, a desktop, a tablet, a mobile device, a phone, anembedded computer, or any other suitable electronic device.

In at least one embodiment, electronic device 1200 may include, withoutlimitation, processor 1210 communicatively coupled to any suitablenumber or kind of components, peripherals, modules, or devices. In atleast one embodiment, processor 1210 is coupled using a bus orinterface, such as a I2C bus, a System Management Bus (“SMBus”), a LowPin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a HighDefinition Audio (“HDA”) bus, a Serial Advance Technology Attachment(“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.),or a Universal Asynchronous Receiver/Transmitter (“UART”) bus. In atleast one embodiment, FIG. 12 illustrates a system, which includesinterconnected hardware devices or “chips”, whereas in otherembodiments, FIG. 12 may illustrate an exemplary SoC. In at least oneembodiment, devices illustrated in FIG. 12 may be interconnected withproprietary interconnects, standardized interconnects (e.g., PCIe) orsome combination thereof. In at least one embodiment, one or morecomponents of FIG. 12 are interconnected using compute express link(CXL) interconnects.

In at least one embodiment, FIG. 12 may include a display 1224, a touchscreen 1225, a touch pad 1230, a Near Field Communications unit (“NEC”)1245, a sensor hub 1240, a thermal sensor 1246, an Express Chipset(“EC”) 1235, a Trusted Platform Module (“TPM”) 1238, BIOS/firmware/flashmemory (“BIOS, FW Flash”) 1222, a DSP 1260, a drive 1220 such as a SolidState Disk (“SSD”) or a Hard Disk Drive (“HDD”), a wireless local areanetwork unit (“WLAN”) 1250, a Bluetooth unit 1252, a Wireless Wide AreaNetwork unit (“WWAN”) 1256, a Global Positioning System (GPS) unit 1255,a camera (“USB 3.0 camera”) 1254 such as a USB 3.0 camera, and/or a LowPower Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1215 implementedin, for example, an LPDDR3 standard. These components may each beimplemented in any suitable manner.

In at least one embodiment, other components may be communicativelycoupled to processor 1210 through components described herein. In atleast one embodiment, an accelerometer 1241, an ambient light sensor(“ALS”) 1242, a compass 1243, and a gyroscope 1244 may becommunicatively coupled to sensor hub 1240. In at least one embodiment,a thermal sensor 1239, a fan 1237, a keyboard 1236, and touch pad 1230may be communicatively coupled to EC 1235. In at least one embodiment,speakers 1263, headphones 1264, and a microphone (“mic”) 1265 may becommunicatively coupled to an audio unit (“audio codec and class D amp”)1262, which may in turn be communicatively coupled to DSP 1260. In atleast one embodiment, audio unit 1262 may include, for example andwithout limitation, an audio coder/decoder (“codec”) and a class Damplifier. In at least one embodiment, a SIM card (“SIM”) 1257 may becommunicatively coupled to WWAN unit 1256. In at least one embodiment,components such as WLAN unit 1250 and Bluetooth unit 1252, as well asWWAN unit 1256 may be implemented in a Next Generation Form Factor(“NGFF”).

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used in systemFIG. 12 for inferencing or predicting operations based, at least inpart, on weight parameters calculated using neural network trainingoperations, neural network functions and/or architectures, or neuralnetwork use cases described herein.

FIG. 13 illustrates a computer system 1300, according to at least oneembodiment. In at least one embodiment, computer system 1300 isconfigured to implement various processes and methods describedthroughout this disclosure.

In at least one embodiment, computer system 1300 comprises, withoutlimitation, at least one central processing unit (“CPU”) 1302 that isconnected to a communication bus 1310 implemented using any suitableprotocol, such as PCI (“Peripheral Component Interconnect”), peripheralcomponent interconnect express (“PCI-Express”), AGP (“AcceleratedGraphics Port”), HyperTransport, or any other bus or point-to-pointcommunication protocol(s). In at least one embodiment, computer system1300 includes, without limitation, a main memory 1304 and control logic(e.g., implemented as hardware, software, or a combination thereof) anddata are stored in main memory 1304, which may take form of randomaccess memory (“RAM”). In at least one embodiment, a network interfacesubsystem (“network interface”) 1322 provides an interface to othercomputing devices and networks for receiving data from and transmittingdata to other systems with computer system 1300.

In at least one embodiment, computer system 1300, in at least oneembodiment, includes, without limitation, input devices 1308, a parallelprocessing system 1312, and display devices 1306 that can be implementedusing a conventional cathode ray tube (“CRT”), a liquid crystal display(“LCD”), a light emitting diode (“LED”) display, a plasma display, orother suitable display technologies. In at least one embodiment, userinput is received from input devices 1308 such as keyboard, mouse,touchpad, microphone, etc. In at least one embodiment, each moduledescribed herein can be situated on a single semiconductor platform toform a processing system.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used in systemFIG. 13 for inferencing or predicting operations based, at least inpart, on weight parameters calculated using neural network trainingoperations, neural network functions and/or architectures, or neuralnetwork use cases described herein.

FIG. 14 illustrates a computer system 1400, according to at least oneembodiment. In at least one embodiment, computer system 1400 includes,without limitation, a computer 1410 and a USB stick 1420. In at leastone embodiment, computer 1410 may include, without limitation, anynumber and type of processor(s) (not shown) and a memory (not shown). Inat least one embodiment, computer 1410 includes, without limitation, aserver, a cloud instance, a laptop, and a desktop computer.

In at least one embodiment, USB stick 1420 includes, without limitation,a processing unit 1430, a USB interface 1440, and USB interface logic1450. In at least one embodiment, processing unit 1430 may be anyinstruction execution system, apparatus, or device capable of executinginstructions. In at least one embodiment, processing unit 1430 mayinclude, without limitation, any number and type of processing cores(not shown). In at least one embodiment, processing unit 1430 comprisesan application specific integrated circuit (“ASIC”) that is optimized toperform any amount and type of operations associated with machinelearning. For instance, in at least one embodiment, processing unit 1430is a tensor processing unit (“TPC”) that is optimized to perform machinelearning inference operations. In at least one embodiment, processingunit 1430 is a vision processing unit (“VPU”) that is optimized toperform machine vision and machine learning inference operations.

In at least one embodiment, USB interface 1440 may be any type of USBconnector or USB socket. For instance, in at least one embodiment, USBinterface 1440 is a USB 3.0 Type-C socket for data and power. In atleast one embodiment, USB interface 1440 is a USB 3.0 Type-A connector.In at least one embodiment, USB interface logic 1450 may include anyamount and type of logic that enables processing unit 1430 to interfacewith devices (e.g., computer 1410) via USB interface 1440.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used in systemFIG. 14 for inferencing or predicting operations based, at least inpart, on weight parameters calculated using neural network trainingoperations, neural network functions and/or architectures, or neuralnetwork use cases described herein.

FIG. 15A illustrates an exemplary architecture in which a plurality ofGPUs 1510(1)-1510(N) is communicatively coupled to a plurality ofmulti-core processors 1505(1)-1505(M) over high-speed links1540(1)-1540(N) (e.g., buses, point-to-point interconnects, etc.). In atleast one embodiment, high-speed links 1540(1)-1540(N) support acommunication throughput of 4 GB/s, 30 GB/s, 80 GB/s or higher. In atleast one embodiment, various interconnect protocols may be usedincluding, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. Invarious figures, “N” and “M” represent positive integers, values ofwhich may be different from figure to figure.

In addition, and in at least one embodiment, two or more of GPUs 1510are interconnected over high-speed links 1529(1)-1529(2), which may beimplemented using similar or different protocols/links than those usedfor high-speed links 1540(1)-1540(N). Similarly, two or more ofmulti-core processors 1505 may be connected over a high-speed link 1528which may be symmetric multi-processor (SMP) buses operating at 20 GB/s,30 GB/s, 120 GB/s or higher. Alternatively, all communication betweenvarious system components shown in FIG. 15A may be accomplished usingsimilar protocols/links (e.g., over a common interconnection fabric).

In at least one embodiment, each multi-core processor 1505 iscommunicatively coupled to a processor memory 1501(1)-1501(M), viamemory interconnects 1526(1)-1526(M), respectively, and each GPU1510(1)-1510(N) is communicatively coupled to GPU memory 1520(1)-1520(N)over GPU memory interconnects 1550(1)-1550(N), respectively. In at leastone embodiment, memory interconnects 1526 and 1550 may utilize similaror different memory access technologies. By way of example, and notlimitation, processor memories 1501(1)-1501(M) and GPU memories 1520 maybe volatile memories such as dynamic random access memories (DRAMs)(including stacked DRAMs), Graphics DDR SDRAM (GDDR) (e.g., GDDR5,GDDR6), or High Bandwidth Memory (HBM) and/or may be non-volatilememories such as 3D XPoint or Nano-Ram. In at least one embodiment, someportion of processor memories 1501 may be volatile memory and anotherportion may be non-volatile memory (e.g., using a two-level memory (2LM)hierarchy).

As described herein, although various multi-core processors 1505 andGPUs 1510 may be physically coupled to a particular memory 1501, 1520,respectively, and/or a unified memory architecture may be implemented inwhich a virtual system address space (also referred to as “effectiveaddress” space) is distributed among various physical memories. Forexample, processor memories 1501(1)-1501(M) may each comprise 64 GB ofsystem memory address space and GPU memories 1520(1)-1520(N) may eachcomprise 32 GB of system memory address space resulting in a total of256 GB addressable memory when M=2 and N=4. Other values for N and M arepossible.

FIG. 15B illustrates additional details for an interconnection between amulti-core processor 1507 and a graphics acceleration module 1546 inaccordance with one exemplary embodiment. In at least one embodiment,graphics acceleration module 1546 may include one or more GPU chipsintegrated on a line card which is coupled to processor 1507 viahigh-speed link 1540 (e.g., a PCIe bus, NVLink, etc.). In at least oneembodiment, graphics acceleration module 1546 may alternatively beintegrated on a package or chip with processor 1507.

In at least one embodiment, processor 1507 includes a plurality of cores1560A-1560D, each with a translation lookaside buffer (“TLB”)1561A-1561D and one or more caches 1562A-1562D. In at least oneembodiment, cores 1560A-1560D may include various other components forexecuting instructions and processing data that are not illustrated. Inat least one embodiment, caches 1562A-1562D may comprise Level 1 (L1)and Level 2 (L2) caches. In addition, one or more shared caches 1556 maybe included in caches 1562A-1562D and shared by sets of cores1560A-1560D. For example, one embodiment of processor 1507 includes 24cores, each with its own L1 cache, twelve shared L2 caches, and twelveshared L3 caches. In this embodiment, one or more L2 and L3 caches areshared by two adjacent cores. In at least one embodiment, processor 1507and graphics acceleration module 1546 connect with system memory 1514,which may include processor memories 1501(1)-1501(M) of FIG. 15A.

In at least one embodiment, coherency is maintained for data andinstructions stored in various caches 1562A-1562D, 1556 and systemmemory 1514 via inter-core communication over a coherence bus 1564. Inat least one embodiment, for example, each cache may have cachecoherency logic/circuitry associated therewith to communicate to overcoherence bus 1564 in response to detected reads or writes to particularcache lines. In at least one embodiment, a cache snooping protocol isimplemented over coherence bus 1564 to snoop cache accesses.

In at least one embodiment, a proxy circuit 1525 communicatively couplesgraphics acceleration module 1546 to coherence bus 1564, allowinggraphics acceleration module 1546 to participate in a cache coherenceprotocol as a peer of cores 1560A-1560D. In particular, in at least oneembodiment, an interface 1535 provides connectivity to proxy circuit1525 over high-speed link 1540 and an interface 1537 connects graphicsacceleration module 1546 to high-speed link 1540.

In at least one embodiment, an accelerator integration circuit 1536provides cache management, memory access, context management, andinterrupt management services on behalf of a plurality of graphicsprocessing engines 1531(1)-1531(N) of graphics acceleration module 1546.In at least one embodiment, graphics processing engines 1531(1)-1531(N)may each comprise a separate GPU. In at least one embodiment, graphicsprocessing engines 1531(1)-1531(N) alternatively may comprise differenttypes of graphics processing engines within a GPU, such as graphicsexecution units, media processing engines (e.g., videoencoders/decoders), samplers, and blit engines. In at least oneembodiment, graphics acceleration module 1546 may be a GPU with aplurality of graphics processing engines 1531(1)-1531(N) or graphicsprocessing engines 1531(1)-1531(N) may be individual GPUs integrated ona common package, line card, or chip.

In at least one embodiment, accelerator integration circuit 1536includes a memory management unit (MMU) 1539 for performing variousmemory management functions such as virtual-to-physical memorytranslations (also referred to as effective-to-real memory translations)and memory access protocols for accessing system memory 1514. In atleast one embodiment, MMU 1539 may also include a translation lookasidebuffer (TLB) (not shown) for caching virtual/effective to physical/realaddress translations. In at least one embodiment, a cache 1538 can storecommands and data for efficient access by graphics processing engines1531(1)-1531(N). In at least one embodiment, data stored in cache 1538and graphics memories 1533(1)-1533(M) is kept coherent with core caches1562A-1562D, 1556 and system memory 1514, possibly using a fetch unit1544. As mentioned, this may be accomplished via proxy circuit 1525 onbehalf of cache 1538 and memories 1533(1)-1533(M) (e.g., sending updatesto cache 1538 related to modifications/accesses of cache lines onprocessor caches 1562A-1562D, 1556 and receiving updates from cache1538).

In at least one embodiment, a set of registers 1545 store context datafor threads executed by graphics processing engines 1531(1)-1531(N) anda context management circuit 1548 manages thread contexts. For example,context management circuit 1548 may perform save and restore operationsto save and restore contexts of various threads during contexts switches(e.g., where a first thread is saved and a second thread is stored sothat a second thread can be execute by a graphics processing engine).For example, on a context switch, context management circuit 1548 maystore current register values to a designated region in memory (e.g.,identified by a context pointer). It may then restore register valueswhen returning to a context. In at least one embodiment, an interruptmanagement circuit 1547 receives and processes interrupts received fromsystem devices.

In at least one embodiment, virtual/effective addresses from a graphicsprocessing engine 1531 are translated to real/physical addresses insystem memory 1514 by MMU 1539. In at least one embodiment, acceleratorintegration circuit 1536 supports multiple (e.g., 4, 8, 16) graphicsaccelerator modules 1546 and/or other accelerator devices. In at leastone embodiment, graphics accelerator module 1546 may be dedicated to asingle application executed on processor 1507 or may be shared betweenmultiple applications. In at least one embodiment, a virtualizedgraphics execution environment is presented in which resources ofgraphics processing engines 1531(1)-1531(N) are shared with multipleapplications or virtual machines (VMs). In at least one embodiment,resources may be subdivided into “slices” which are allocated todifferent VMs and/or applications based on processing requirements andpriorities associated with VMs and/or applications.

In at least one embodiment, accelerator integration circuit 1536performs as a bridge to a system for graphics acceleration module 1546and provides address translation and system memory cache services. Inaddition, in at least one embodiment, accelerator integration circuit1536 may provide virtualization facilities for a host processor tomanage virtualization of graphics processing engines 1531(1)-1531(N),interrupts, and memory management.

In at least one embodiment, because hardware resources of graphicsprocessing engines 1531(1)-1531(N) are mapped explicitly to a realaddress space seen by host processor 1507, any host processor canaddress these resources directly using an effective address value. In atleast one embodiment, one function of accelerator integration circuit1536 is physical separation of graphics processing engines1531(1)-1531(N) so that they appear to a system as independent units.

In at least one embodiment, one or more graphics memories1533(1)-1533(M) are coupled to each of graphics processing engines1531(1)-1531(N), respectively and N=M. In at least one embodiment,graphics memories 1533(1)-1533(M) store instructions and data beingprocessed by each of graphics processing engines 1531(1)-1531(N). In atleast one embodiment, graphics memories 1533(1)-1533(M) may be volatilememories such as DRAMs (including stacked DRAMs), GDDR memory (e.g.,GDDR5, GDDR6), or HBM, and/or may be non-volatile memories such as 3DXPoint or Nano-Ram.

In at least one embodiment, to reduce data traffic over high-speed link1540, biasing techniques can be used to ensure that data stored ingraphics memories 1533(1)-1533(M) is data that will be used mostfrequently by graphics processing engines 1531(1)-1531(N) and not usedby cores 1560A-1560D (at least not frequently). Similarly, in at leastone embodiment, a biasing mechanism attempts to keep data needed bycores (and not graphics processing engines 1531(1)-1531(N)) withincaches 1562A-1562D, 1556 and system memory 1514.

FIG. 15C illustrates another exemplary embodiment in which acceleratorintegration circuit 1536 is integrated within processor 1507. In thisembodiment, graphics processing engines 1531(1)-1531(N) communicatedirectly over high-speed link 1540 to accelerator integration circuit1536 via interface 1537 and interface 1535 (which, again, may be anyform of bus or interface protocol). In at least one embodiment,accelerator integration circuit 1536 may perform similar operations asthose described with respect to FIG. 15B, but potentially at a higherthroughput given its close proximity to coherence bus 1564 and caches1562A-1562D, 1556. In at least one embodiment, an acceleratorintegration circuit supports different programming models including adedicated-process programming model (no graphics acceleration modulevirtualization) and shared programming models (with virtualization),which may include programming models which are controlled by acceleratorintegration circuit 1536 and programming models which are controlled bygraphics acceleration module 1546.

In at least one embodiment, graphics processing engines 1531(1)-1531(N)are dedicated to a single application or process under a singleoperating system. In at least one embodiment, a single application canfunnel other application requests to graphics processing engines1531(1)-1531(N), providing virtualization within a VM/partition.

In at least one embodiment, graphics processing engines 1531(1)-1531(N),may be shared by multiple VM/application partitions. In at least oneembodiment, shared models may use a system hypervisor to virtualizegraphics processing engines 1531(1)-1531(N) to allow access by eachoperating system. In at least one embodiment, for single-partitionsystems without a hypervisor, graphics processing engines1531(1)-1531(N) are owned by an operating system. In at least oneembodiment, an operating system can virtualize graphics processingengines 1531(1)-1531(N) to provide access to each process orapplication.

In at least one embodiment, graphics acceleration module 1546 or anindividual graphics processing engine 1531(1)-1531(N) selects a processelement using a process handle. In at least one embodiment, processelements are stored in system memory 1514 and are addressable using aneffective address to real address translation technique describedherein. In at least one embodiment, a process handle may be animplementation-specific value provided to a host process whenregistering its context with graphics processing engine 1531(1)-1531(N)(that is, calling system software to add a process element to a processelement linked list). In at least one embodiment, a lower 16-bits of aprocess handle may be an offset of a process element within a processelement linked list.

FIG. 15D illustrates an exemplary accelerator integration slice 1590. Inat least one embodiment, a “slice” comprises a specified portion ofprocessing resources of accelerator integration circuit 1536. In atleast one embodiment, an application is effective address space 1582within system memory 1514 stores process elements 1583. In at least oneembodiment, process elements 1583 are stored in response to GPUinvocations 1581 from applications 1580 executed on processor 1507. Inat least one embodiment, a process element 1583 contains process statefor corresponding application 1580. In at least one embodiment, a workdescriptor (WD) 1584 contained in process element 1583 can be a singlejob requested by an application or may contain a pointer to a queue ofjobs. In at least one embodiment, WD 1584 is a pointer to a job requestqueue in an application's effective address space 1582.

In at least one embodiment, graphics acceleration module 1546 and/orindividual graphics processing engines 1531(1)-1531(N) can be shared byall or a subset of processes in a system. In at least one embodiment, aninfrastructure for setting up process states and sending a WD 1584 to agraphics acceleration module 1546 to start a job in a virtualizedenvironment may be included.

In at least one embodiment, a dedicated-process programming model isimplementation-specific. In at least one embodiment, in this model, asingle process owns graphics acceleration module 1546 or an individualgraphics processing engine 1531. In at least one embodiment, whengraphics acceleration module 1546 is owned by a single process, ahypervisor initializes accelerator integration circuit 1536 for anowning partition and an operating system initializes acceleratorintegration circuit 1536 for an owning process when graphicsacceleration module 1546 is assigned.

In at least one embodiment, in operation, a WD fetch unit 1591 inaccelerator integration slice 1590 fetches next WD 1584, which includesan indication of work to be done by one or more graphics processingengines of graphics acceleration module 1546. In at least oneembodiment, data from WD 1584 may be stored in registers 1545 and usedby MMU 1539, interrupt management circuit 1547 and/or context managementcircuit 1548 as illustrated. For example, one embodiment of MMU 1539includes segment/page walk circuitry for accessing segment/page tables1586 within an OS virtual address space 1585. In at least oneembodiment, interrupt management circuit 1547 may process interruptevents 1592 received from graphics acceleration module 1546. In at leastone embodiment, when performing graphics operations, an effectiveaddress 1593 generated by a graphics processing engine 1531(1)-1531(N)is translated to a real address by MMU 1539.

In at least one embodiment, registers 1545 are duplicated for eachgraphics processing engine 1531(1)-1531(N) and/or graphics accelerationmodule 1546 and may be initialized by a hypervisor or an operatingsystem. In at least one embodiment, each of these duplicated registersmay be included in an accelerator integration slice 1590. Exemplaryregisters that may be initialized by a hypervisor are shown in Table 1.

TABLE 1 Hypervisor Initialized Registers Register # Description 1 SliceControl Register 2 Real Address (RA) Scheduled Processes Area Pointer 3Authority Mask Override Register 4 Interrupt Vector Table Entry Offset 5Interrupt Vector Table Entry Limit 6 State Register 7 Logical PartitionID 8 Real address (RA) Hypervisor Accelerator Utilization Record Pointer9 Storage Description Register

Exemplary registers that may be initialized by an operating system areshown in Table 2.

TABLE 2 Operating System Initialized Registers Register # Description 1Process and Thread Identification 2 Effective Address (EA) ContextSave/Restore Pointer 3 Virtual Address (VA) Accelerator UtilizationRecord Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5Authority Mask 6 Work descriptor

In at least one embodiment, each WD 1584 is specific to a particulargraphics acceleration module 1546 and/or graphics processing engines1531(1)-1531(N). In at least one embodiment, it contains all informationrequired by a graphics processing engine 1531(1)-1531(N) to do work, orit can be a pointer to a memory location where an application has set upa command queue of work to be completed.

FIG. 15E illustrates additional details for one exemplary embodiment ofa shared model. This embodiment includes a hypervisor real address space1598 in which a process element list 1599 is stored. In at least oneembodiment, hypervisor real address space 1598 is accessible via ahypervisor 1596 which virtualizes graphics acceleration module enginesfor operating system 1595.

In at least one embodiment, shared programming models allow for all or asubset of processes from all or a subset of partitions in a system touse a graphics acceleration module 1546. In at least one embodiment,there are two programming models where graphics acceleration module 1546is shared by multiple processes and partitions, namely time-slicedshared and graphics directed shared.

In at least one embodiment, in this model, system hypervisor 1596 ownsgraphics acceleration module 1546 and makes its function available toall operating systems 1595. In at least one embodiment, for a graphicsacceleration module 1546 to support virtualization by system hypervisor1596, graphics acceleration module 1546 may adhere to certainrequirements, such as (1) an application's job request must beautonomous (that is, state does not need to be maintained between jobs),or graphics acceleration module 1546 must provide a context save andrestore mechanism, (2) an application's job request is guaranteed bygraphics acceleration module 1546 to complete in a specified amount oftime, including any translation faults, or graphics acceleration module1546 provides an ability to preempt processing of a job, and (3)graphics acceleration module 1546 must be guaranteed fairness betweenprocesses when operating in a directed shared programming model.

In at least one embodiment, application 1580 is required to make anoperating system 1595 system call with a graphics acceleration moduletype, a work descriptor (WD), an authority mask register (AMR) value,and a context save/restore area pointer (CSRP). In at least oneembodiment, graphics acceleration module type describes a targetedacceleration function for a system call. In at least one embodiment,graphics acceleration module type may be a system-specific value. In atleast one embodiment, WD is formatted specifically for graphicsacceleration module 1546 and can be in a form of a graphics accelerationmodule 1546 command, an effective address pointer to a user-definedstructure, an effective address pointer to a queue of commands, or anyother data structure to describe work to be done by graphicsacceleration module 1546.

In at least one embodiment, an AMR value is an AMR state to use for acurrent process. In at least one embodiment, a value passed to anoperating system is similar to an application setting an AMR. In atleast one embodiment, if accelerator integration circuit 1536 (notshown) and graphics acceleration module 1546 implementations do notsupport a User Authority Mask Override Register (UAMOR), an operatingsystem may apply a current UAMOR value to an AMR value before passing anAMR in a hypervisor call. In at least one embodiment, hypervisor 1596may optionally apply a current Authority Mask Override Register (AMOR)value before placing an AMR into process element 1583. In at least oneembodiment, CSRP is one of registers 1545 containing an effectiveaddress of an area in an application's effective address space 1582 forgraphics acceleration module 1546 to save and restore context state. Inat least one embodiment, this pointer is optional if no state isrequired to be saved between jobs or when a job is preempted. In atleast one embodiment, context save/restore area may be pinned systemmemory.

Upon receiving a system call, operating system 1595 may verify thatapplication 1580 has registered and been given authority to use graphicsacceleration module 1546. In at least one embodiment, operating system1595 then calls hypervisor 1596 with information shown in Table 3.

TABLE 3 OS to Hypervisor Call Parameters Parameter # Description 1 Awork descriptor (WD) 2 An Authority Mask Register (AMR) value(potentially masked) 3 An effective address (EA) Context Save/RestoreArea Pointer (CSRP) 4 A process ID (PID) and optional thread ID (TID) 5A virtual address (VA) accelerator utilization record pointer (AURP) 6Virtual address of storage segment table pointer (SSTP) 7 A logicalinterrupt service number (LISN)

In at least one embodiment, upon receiving a hypervisor call, hypervisor1596 verifies that operating system 1595 has registered and been givenauthority to use graphics acceleration module 1546. In at least oneembodiment, hypervisor 1596 then puts process element 1583 into aprocess element linked list for a corresponding graphics accelerationmodule 1546 type. In at least one embodiment, a process element mayinclude information shown in Table 4.

TABLE 4 Process Element Information Element # Description  1 A workdescriptor (WD)  2 An Authority Mask Register (AMR) value (potentiallymasked).  3 An effective address (EA) Context Save/Restore Area Pointer(CSRP)  4 A process ID (PID) and optional thread ID (TID)  5 A virtualaddress (VA) accelerator utilization record pointer (AURP)  6 Virtualaddress of storage segment table pointer (SSTP)  7 A logical interruptservice number (LISN)  8 Interrupt vector table, derived from hypervisorcall parameters  9 A state register (SR) value 10 A logical partition ID(LPID) 11 A real address (RA) hypervisor accelerator utilization recordpointer 12 Storage Descriptor Register (SDR)

In at least one embodiment, hypervisor initializes a plurality ofaccelerator integration slice 1590 registers 1545.

As illustrated in FIG. 15F, in at least one embodiment, a unified memoryis used, addressable via a common virtual memory address space used toaccess physical processor memories 1501(1)-1501(N) and GPU memories1520(1)-1520(N). In this implementation, operations executed on GPUs1510(1)-1510(N) utilize a same virtual/effective memory address space toaccess processor memories 1501(1)-1501(M) and vice versa, therebysimplifying programmability. In at least one embodiment, a first portionof a virtual/effective address space is allocated to processor memory1501(1), a second portion to second processor memory 1501(N), a thirdportion to GPU memory 1520(1), and so on. In at least one embodiment, anentire virtual/effective memory space (sometimes referred to as aneffective address space) is thereby distributed across each of processormemories 1501 and GPU memories 1520, allowing any processor or GPU toaccess any physical memory with a virtual address mapped to that memory.

In at least one embodiment, bias/coherence management circuitry1594A-1594E within one or more of MMUs 1539A-1539E ensures cachecoherence between caches of one or more host processors (e.g., 1505) andGPUs 1510 and implements biasing techniques indicating physical memoriesin which certain types of data should be stored. In at least oneembodiment, while multiple instances of bias/coherence managementcircuitry 1594A-1594E are illustrated in FIG. 15F, bias/coherencecircuitry may be implemented within an MMU of one or more hostprocessors 1505 and/or within accelerator integration circuit 1536.

One embodiment allows GPU memories 1520 to be mapped as part of systemmemory, and accessed using shared virtual memory (SVM) technology, butwithout suffering performance drawbacks associated with full systemcache coherence. In at least one embodiment, an ability for GPU memories1520 to be accessed as system memory without onerous cache coherenceoverhead provides a beneficial operating environment for GPU offload. Inat least one embodiment, this arrangement allows software of hostprocessor 1505 to setup operands and access computation results, withoutoverhead of tradition I/O DMA data copies. In at least one embodiment,such traditional copies involve driver calls, interrupts and memorymapped I/O (MMIO) accesses that are all inefficient relative to simplememory accesses. In at least one embodiment, an ability to access GPUmemories 1520 without cache coherence overheads can be critical toexecution time of an offloaded computation. In at least one embodiment,in cases with substantial streaming write memory traffic, for example,cache coherence overhead can significantly reduce an effective writebandwidth seen by a GPU 1510. In at least one embodiment, efficiency ofoperand setup, efficiency of results access, and efficiency of GPUcomputation may play a role in determining effectiveness of a GPUoffload.

In at least one embodiment, selection of GPU bias and host processorbias is driven by a bias tracker data structure. In at least oneembodiment, a bias table may be used, for example, which may be apage-granular structure (e.g., controlled at a granularity of a memorypage) that includes 1 or 2 bits per GPU-attached memory page. In atleast one embodiment, a bias table may be implemented in a stolen memoryrange of one or more GPU memories 1520, with or without a bias cache ina GPU 1510 (e.g., to cache frequently/recently used entries of a biastable). Alternatively, in at least one embodiment, an entire bias tablemay be maintained within a GPU.

In at least one embodiment, a bias table entry associated with eachaccess to a GPU attached memory 1520 is accessed prior to actual accessto a GPU memory, causing following operations. In at least oneembodiment, local requests from a GPU 1510 that find their page in GPUbias are forwarded directly to a corresponding GPU memory 1520. In atleast one embodiment, local requests from a GPU that find their page inhost bias are forwarded to processor 1505 (e.g., over a high-speed linkas described herein). In at least one embodiment, requests fromprocessor 1505 that find a requested page in host processor biascomplete a request like a normal memory read. Alternatively, requestsdirected to a GPU-biased page may be forwarded to a GPU 1510. In atleast one embodiment, a GPU may then transition a page to a hostprocessor bias if it is not currently using a page. In at least oneembodiment, a bias state of a page can be changed either by asoftware-based mechanism, a hardware-assisted software-based mechanism,or, for a limited set of cases, a purely hardware-based mechanism.

In at least one embodiment, one mechanism for changing bias stateemploys an API call (e.g., OpenCL), which, in turn, calls a GPU's devicedriver which, in turn, sends a message (or enqueues a commanddescriptor) to a GPU directing it to change a bias state and, for sometransitions, perform a cache flushing operation in a host. In at leastone embodiment, a cache flushing operation is used for a transition fromhost processor 1505 bias to GPU bias, but is not for an oppositetransition.

In at least one embodiment, cache coherency is maintained by temporarilyrendering GPU-biased pages uncacheable by host processor 1505. In atleast one embodiment, to access these pages, processor 1505 may requestaccess from GPU 1510, which may or may not grant access right away. Inat least one embodiment, thus, to reduce communication between processor1505 and GPU 1510 it is beneficial to ensure that GPU-biased pages arethose which are required by a GPU but not host processor 1505 and viceversa.

Hardware structure(s) 115 are used to perform one or more embodiments.Details regarding a hardware structure(s) 115 may be provided herein inconjunction with FIGS. 1A and/or 1B.

FIG. 16 illustrates exemplary integrated circuits and associatedgraphics processors that may be fabricated using one or more IP cores,according to various embodiments described herein. In addition to whatis illustrated, other logic and circuits may be included in at least oneembodiment, including additional graphics processors/cores, peripheralinterface controllers, or general-purpose processor cores.

FIG. 16 is a block diagram illustrating an exemplary system on a chipintegrated circuit 1600 that may be fabricated using one or more IPcores, according to at least one embodiment. In at least one embodiment,integrated circuit 1600 includes one or more application processor(s)1605 (e.g., CPUs), at least one graphics processor 1610, and mayadditionally include an image processor 1615 and/or a video processor1620, any of which may be a modular IP core. In at least one embodiment,integrated circuit 1600 includes peripheral or bus logic including a USBcontroller 1625, a UART controller 1630, an SPI/SDIO controller 1635,and an I22S/I22C controller 1640. In at least one embodiment, integratedcircuit 1600 can include a display device 1645 coupled to one or more ofa high-definition multimedia interface (HDMI) controller 1650 and amobile industry processor interface (MIPI) display interface 1655. In atleast one embodiment, storage may be provided by a flash memorysubsystem 1660 including flash memory and a flash memory controller. Inat least one embodiment, a memory interface may be provided via a memorycontroller 1665 for access to SDRAM or SRAM memory devices. In at leastone embodiment, some integrated circuits additionally include anembedded security engine 1670.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used inintegrated circuit 1600 for inferencing or predicting operations based,at least in part, on weight parameters calculated using neural networktraining operations, neural network functions and/or architectures, orneural network use cases described herein.

FIGS. 17A-17B illustrate exemplary integrated circuits and associatedgraphics processors that may be fabricated using one or more IP cores,according to various embodiments described herein. In addition to whatis illustrated, other logic and circuits may be included in at least oneembodiment, including additional graphics processors/cores, peripheralinterface controllers, or general-purpose processor cores.

FIGS. 17A-17B are block diagrams illustrating exemplary graphicsprocessors for use within an SoC, according to embodiments describedherein. FIG. 17A illustrates an exemplary graphics processor 1710 of asystem on a chip integrated circuit that may be fabricated using one ormore IP cores, according to at least one embodiment. FIG. 17Billustrates an additional exemplary graphics processor 1740 of a systemon a chip integrated circuit that may be fabricated using one or more IPcores, according to at least one embodiment. In at least one embodiment,graphics processor 1710 of FIG. 17A is a low power graphics processorcore. In at least one embodiment, graphics processor 1740 of FIG. 17B isa higher performance graphics processor core. In at least oneembodiment, each of graphics processors 1710, 1740 can be variants ofgraphics processor 1610 of FIG. 16.

In at least one embodiment, graphics processor 1710 includes a vertexprocessor 1705 and one or more fragment processor(s) 1715A-1715N (e.g.,1715A, 1715B, 1715C, 1715D, through 1715N-1, and 1715N). In at least oneembodiment, graphics processor 1710 can execute different shaderprograms via separate logic, such that vertex processor 1705 isoptimized to execute operations for vertex shader programs, while one ormore fragment processor(s) 1715A-1715N execute fragment (e.g., pixel)shading operations for fragment or pixel shader programs. In at leastone embodiment, vertex processor 1705 performs a vertex processing stageof a 3D graphics pipeline and generates primitives and vertex data. Inat least one embodiment, fragment processor(s) 1715A-1715N use primitiveand vertex data generated by vertex processor 1705 to produce aframebuffer that is displayed on a display device. In at least oneembodiment, fragment processor(s) 1715A-1715N are optimized to executefragment shader programs as provided for in an OpenGL API, which may beused to perform similar operations as a pixel shader program as providedfor in a Direct 3D API.

In at least one embodiment, graphics processor 1710 additionallyincludes one or more memory management units (MMUs) 1720A-1720B,cache(s) 1725A-1725B, and circuit interconnect(s) 1730A-1730B. In atleast one embodiment, one or more MMU(s) 1720A-1720B provide for virtualto physical address mapping for graphics processor 1710, including forvertex processor 1705 and/or fragment processor(s) 1715A-1715N, whichmay reference vertex or image/texture data stored in memory, in additionto vertex or image/texture data stored in one or more cache(s)1725A-1725B. In at least one embodiment, one or more MMU(s) 1720A-1720Bmay be synchronized with other MMUs within a system, including one ormore MMUs associated with one or more application processor(s) 1605,image processors 1015, and/or video processors 1620 of FIG. 16, suchthat each processor 1605-1620 can participate in a shared or unifiedvirtual memory system. In at least one embodiment, one or more circuitinterconnect(s) 1730A-1730B enable graphics processor 1710 to interfacewith other IP cores within SoC, either via an internal bus of SoC or viaa direct connection.

In at least one embodiment, graphics processor 1740 includes one or moreshader core(s) 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E,1755F, through 1755N-1, and 1755N) as shown in FIG. 17B, which providesfor a unified shader core architecture in which a single core or type orcore can execute all types of programmable shader code, including shaderprogram code to implement vertex shaders, fragment shaders, and/orcompute shaders. In at least one embodiment, a number of shader corescan vary. In at least one embodiment, graphics processor 1740 includesan inter-core task manager 1745, which acts as a thread dispatcher todispatch execution threads to one or more shader cores 1755A-1755N and atiling unit 1758 to accelerate tiling operations for tile-basedrendering, in which rendering operations for a scene are subdivided inimage space, for example to exploit local spatial coherence within ascene or to optimize use of internal caches.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used inintegrated circuit 11A and/or 11B for inferencing or predictingoperations based, at least in part, on weight parameters calculatedusing neural network training operations, neural network functionsand/or architectures, or neural network use cases described herein.

FIGS. 18A-18B illustrate additional exemplary graphics processor logicaccording to embodiments described herein. FIG. 18A illustrates agraphics core 1800 that may be included within graphics processor 1610of FIG. 16, in at least one embodiment, and may be a unified shader core1755A-1755N as in FIG. 17B in at least one embodiment. FIG. 18Billustrates a highly-parallel general-purpose graphics processing unit(“GPGPU”) 1830 suitable for deployment on a multi-chip module in atleast one embodiment.

In at least one embodiment, graphics core 1800 includes a sharedinstruction cache 1802, a texture unit 1818, and a cache/shared memory1820 that are common to execution resources within graphics core 1800.In at least one embodiment, graphics core 1800 can include multipleslices 1801A-1801N or a partition for each core, and a graphicsprocessor can include multiple instances of graphics core 1800. In atleast one embodiment, slices 1801A-1801N can include support logicincluding a local instruction cache 1804A-1804N, a thread scheduler1806A-1806N, a thread dispatcher 1808A-1808N, and a set of registers1810A-1810N. In at least one embodiment, slices 1801A-1801N can includea set of additional function units (AFUs 1812A-1812N), floating-pointunits (FPUs 1814A-1814N), integer arithmetic logic units (ALUs1816A-1816N), address computational units (ACUs 1813A-1813N),double-precision floating-point units (DPFPUs 1815A-1815N), and matrixprocessing units (MPUs 1817A-1817N).

In at least one embodiment, FPUs 1814A-1814N can performsingle-precision (32-bit) and half-precision (16-bit) floating pointoperations, while DPFPUs 1815A-1815N perform double precision (64-bit)floating point operations. In at least one embodiment, ALUs 1816A-1816Ncan perform variable precision integer operations at 8-bit, 16-bit, and32-bit precision, and can be configured for mixed precision operations.In at least one embodiment, MPUs 1817A-1817N can also be configured formixed precision matrix operations, including half-precision floatingpoint and 8-bit integer operations. In at least one embodiment, MPUs1817-1817N can perform a variety of matrix operations to acceleratemachine learning application frameworks, including enabling support foraccelerated general matrix to matrix multiplication (GEMM). In at leastone embodiment, AFUs 1812A-1812N can perform additional logic operationsnot supported by floating-point or integer units, includingtrigonometric operations (e.g., sine, cosine, etc.).

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used in graphicscore 1800 for inferencing or predicting operations based, at least inpart, on weight parameters calculated using neural network trainingoperations, neural network functions and/or architectures, or neuralnetwork use cases described herein.

FIG. 18B illustrates a general-purpose processing unit (GPGPU) 1830 thatcan be configured to enable highly-parallel compute operations to beperformed by an array of graphics processing units, in at least oneembodiment. In at least one embodiment, GPGPU 1830 can be linkeddirectly to other instances of GPGPU 1830 to create a multi-GPU clusterto improve training speed for deep neural networks. In at least oneembodiment, GPGPU 1830 includes a host interface 1832 to enable aconnection with a host processor. In at least one embodiment, hostinterface 1832 is a PCI Express interface. In at least one embodiment,host interface 1832 can be a vendor-specific communications interface orcommunications fabric. In at least one embodiment, GPGPU 1830 receivescommands from a host processor and uses a global scheduler 1834 todistribute execution threads associated with those commands to a set ofcompute clusters 1836A-1836H. In at least one embodiment, computeclusters 1836A-1836H share a cache memory 1838. In at least oneembodiment, cache memory 1838 can serve as a higher-level cache forcache memories within compute clusters 1836A-1836H.

In at least one embodiment, GPGPU 1830 includes memory 1844A-1844Bcoupled with compute clusters 1836A-1836H via a set of memorycontrollers 1842A-1842B. In at least one embodiment, memory 1844A-1844Bcan include various types of memory devices including dynamic randomaccess memory (DRAM) or graphics random access memory, such assynchronous graphics random access memory (SGRAM), including graphicsdouble data rate (GDDR) memory.

In at least one embodiment, compute clusters 1836A-1836H each include aset of graphics cores, such as graphics core 1800 of FIG. 18A, which caninclude multiple types of integer and floating point logic units thatcan perform computational operations at a range of precisions includingsuited for machine learning computations. For example, in at least oneembodiment, at least a subset of floating point units in each of computeclusters 1836A-1836H can be configured to perform 16-bit or 32-bitfloating point operations, while a different subset of floating pointunits can be configured to perform 64-bit floating point operations.

In at least one embodiment, multiple instances of GPGPU 1830 can beconfigured to operate as a compute cluster. In at least one embodiment,communication used by compute clusters 1836A-1836H for synchronizationand data exchange varies across embodiments. In at least one embodiment,multiple instances of GPGPU 1830 communicate over host interface 1832.In at least one embodiment, GPGPU 1830 includes an I/O hub 1839 thatcouples GPGPU 1830 with a GPU link 1840 that enables a direct connectionto other instances of GPGPU 1830. In at least one embodiment, GPU link1840 is coupled to a dedicated GPU-to-GPU bridge that enablescommunication and synchronization between multiple instances of GPGPU1830. In at least one embodiment, GPU link 1840 couples with ahigh-speed interconnect to transmit and receive data to other GPGPUs orparallel processors. In at least one embodiment, multiple instances ofGPGPU 1830 are located in separate data processing systems andcommunicate via a network device that is accessible via host interface1832. In at least one embodiment GPU link 1840 can be configured toenable a connection to a host processor in addition to or as analternative to host interface 1832.

In at least one embodiment, GPGPU 1830 can be configured to train neuralnetworks. In at least one embodiment, GPGPU 1830 can be used within aninferencing platform. In at least one embodiment, in which GPGPU 1830 isused for inferencing, GPGPU 1830 may include fewer compute clusters1836A-1836H relative to when GPGPU 1830 is used for training a neuralnetwork. In at least one embodiment, memory technology associated withmemory 1844A-1844B may differ between inferencing and trainingconfigurations, with higher bandwidth memory technologies devoted totraining configurations. In at least one embodiment, an inferencingconfiguration of GPGPU 1830 can support inferencing specificinstructions. For example, in at least one embodiment, an inferencingconfiguration can provide support for one or more 8-bit integer dotproduct instructions, which may be used during inferencing operationsfor deployed neural networks.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used in GPGPU1830 for inferencing or predicting operations based, at least in part,on weight parameters calculated using neural network trainingoperations, neural network functions and/or architectures, or neuralnetwork use cases described herein.

FIG. 19 is a block diagram illustrating a computing system 1900according to at least one embodiment. In at least one embodiment,computing system 1900 includes a processing subsystem 1901 having one ormore processor(s) 1902 and a system memory 1904 communicating via aninterconnection path that may include a memory hub 1905. In at least oneembodiment, memory hub 1905 may be a separate component within a chipsetcomponent or may be integrated within one or more processor(s) 1902. Inat least one embodiment, memory hub 1905 couples with an I/O subsystem1911 via a communication link 1906. In at least one embodiment, I/Osubsystem 1911 includes an I/O hub 1907 that can enable computing system1900 to receive input from one or more input device(s) 1908. In at leastone embodiment, I/O hub 1907 can enable a display controller, which maybe included in one or more processor(s) 1902, to provide outputs to oneor more display device(s) 1910A. In at least one embodiment, one or moredisplay device(s) 1910A coupled with I/O hub 1907 can include a local,internal, or embedded display device.

In at least one embodiment, processing subsystem 1901 includes one ormore parallel processor(s) 1912 coupled to memory hub 1905 via a bus orother communication link 1913. In at least one embodiment, communicationlink 1913 may use one of any number of standards based communicationlink technologies or protocols, such as, but not limited to PCI Express,or may be a vendor-specific communications interface or communicationsfabric. In at least one embodiment, one or more parallel processor(s)1912 form a computationally focused parallel or vector processing systemthat can include a large number of processing cores and/or processingclusters, such as a many-integrated core (MIC) processor. In at leastone embodiment, some or all of parallel processor(s) 1912 form agraphics processing subsystem that can output pixels to one of one ormore display device(s) 1910A coupled via I/O Hub 1907. In at least oneembodiment, parallel processor(s) 1912 can also include a displaycontroller and display interface (not shown) to enable a directconnection to one or more display device(s) 1910B.

In at least one embodiment, a system storage unit 1914 can connect toI/O hub 1907 to provide a storage mechanism for computing system 1900.In at least one embodiment, an I/O switch 1916 can be used to provide aninterface mechanism to enable connections between I/O hub 1907 and othercomponents, such as a network adapter 1918 and/or a wireless networkadapter 1919 that may be integrated into platform, and various otherdevices that can be added via one or more add-in device(s) 1920. In atleast one embodiment, network adapter 1918 can be an Ethernet adapter oranother wired network adapter. In at least one embodiment, wirelessnetwork adapter 1919 can include one or more of a Wi-Fi, Bluetooth, nearfield communication (NFC), or other network device that includes one ormore wireless radios.

In at least one embodiment, computing system 1900 can include othercomponents not explicitly shown, including USB or other portconnections, optical storage drives, video capture devices, and like,may also be connected to I/O hub 1907. In at least one embodiment,communication paths interconnecting various components in FIG. 19 may beimplemented using any suitable protocols, such as PCI (PeripheralComponent Interconnect) based protocols (e.g., PCI-Express), or otherbus or point-to-point communication interfaces and/or protocol(s), suchas NV-Link high-speed interconnect, or interconnect protocols.

In at least one embodiment, parallel processor(s) 1912 incorporatecircuitry optimized for graphics and video processing, including, forexample, video output circuitry, and constitutes a graphics processingunit (GPU). In at least one embodiment, parallel processor(s) 1912incorporate circuitry optimized for general purpose processing. In atleast embodiment, components of computing system 1900 may be integratedwith one or more other system elements on a single integrated circuit.For example, in at least one embodiment, parallel processor(s) 1912,memory hub 1905, processor(s) 1902, and I/O hub 1907 can be integratedinto a system on chip (SoC) integrated circuit. In at least oneembodiment, components of computing system 1900 can be integrated into asingle package to form a system in package (SIP) configuration. In atleast one embodiment, at least a portion of components of computingsystem 1900 can be integrated into a multi-chip module (MCM), which canbe interconnected with other multi-chip modules into a modular computingsystem.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used computingsystem 1900 of FIG. 19 for inferencing or predicting operations based,at least in part, on weight parameters calculated using neural networktraining operations, neural network functions and/or architectures, orneural network use cases described herein.

Processors

FIG. 20A illustrates a parallel processor 2000 according to at least oneembodiment. In at least one embodiment, various components of parallelprocessor 2000 may be implemented using one or more integrated circuitdevices, such as programmable processors, application specificintegrated circuits (ASICs), or field programmable gate arrays (FPGA).In at least one embodiment, illustrated parallel processor 2000 is avariant of one or more parallel processor(s) 1912 shown in FIG. 19according to an exemplary embodiment.

In at least one embodiment, parallel processor 2000 includes a parallelprocessing unit 2002. In at least one embodiment, parallel processingunit 2002 includes an I/O unit 2004 that enables communication withother devices, including other instances of parallel processing unit2002. In at least one embodiment, I/O unit 2004 may be directlyconnected to other devices. In at least one embodiment, I/O unit 2004connects with other devices via use of a hub or switch interface, suchas a memory hub 2005. In at least one embodiment, connections betweenmemory hub 2005 and I/O unit 2004 form a communication link 2013. In atleast one embodiment, I/O unit 2004 connects with a host interface 2006and a memory crossbar 2016, where host interface 2006 receives commandsdirected to performing processing operations and memory crossbar 2016receives commands directed to performing memory operations.

In at least one embodiment, when host interface 2006 receives a commandbuffer via I/O unit 2004, host interface 2006 can direct work operationsto perform those commands to a front end 2008. In at least oneembodiment, front end 2008 couples with a scheduler 2010, which isconfigured to distribute commands or other work items to a processingcluster array 2012. In at least one embodiment, scheduler 2010 ensuresthat processing cluster array 2012 is properly configured and in a validstate before tasks are distributed to a cluster of processing clusterarray 2012. In at least one embodiment, scheduler 2010 is implementedvia firmware logic executing on a microcontroller. In at least oneembodiment, microcontroller implemented scheduler 2010 is configurableto perform complex scheduling and work distribution operations at coarseand fine granularity, enabling rapid preemption and context switching ofthreads executing on processing array 2012. In at least one embodiment,host software can prove workloads for scheduling on processing clusterarray 2012 via one of multiple graphics processing paths. In at leastone embodiment, workloads can then be automatically distributed acrossprocessing array cluster 2012 by scheduler 2010 logic within amicrocontroller including scheduler 2010.

In at least one embodiment, processing cluster array 2012 can include upto “N” processing clusters (e.g., cluster 2014A, cluster 2014B, throughcluster 2014N), where “N” represents a positive integer (which may be adifferent integer “N” than used in other figures). In at least oneembodiment, each cluster 2014A-2014N of processing cluster array 2012can execute a large number of concurrent threads. In at least oneembodiment, scheduler 2010 can allocate work to clusters 2014A-2014N ofprocessing cluster array 2012 using various scheduling and/or workdistribution algorithms, which may vary depending on workload arisingfor each type of program or computation. In at least one embodiment,scheduling can be handled dynamically by scheduler 2010, or can beassisted in part by compiler logic during compilation of program logicconfigured for execution by processing cluster array 2012. In at leastone embodiment, different clusters 2014A-2014N of processing clusterarray 2012 can be allocated for processing different types of programsor for performing different types of computations.

In at least one embodiment, processing cluster array 2012 can beconfigured to perform various types of parallel processing operations.In at least one embodiment, processing cluster array 2012 is configuredto perform general-purpose parallel compute operations. For example, inat least one embodiment, processing cluster array 2012 can include logicto execute processing tasks including filtering of video and/or audiodata, performing modeling operations, including physics operations, andperforming data transformations.

In at least one embodiment, processing cluster array 2012 is configuredto perform parallel graphics processing operations. In at least oneembodiment, processing cluster array 2012 can include additional logicto support execution of such graphics processing operations, includingbut not limited to, texture sampling logic to perform textureoperations, as well as tessellation logic and other vertex processinglogic. In at least one embodiment, processing cluster array 2012 can beconfigured to execute graphics processing related shader programs suchas, but not limited to, vertex shaders, tessellation shaders, geometryshaders, and pixel shaders. In at least one embodiment, parallelprocessing unit 2002 can transfer data from system memory via I/O unit2004 for processing. In at least one embodiment, during processing,transferred data can be stored to on-chip memory (e.g., parallelprocessor memory 2022) during processing, then written back to systemmemory.

In at least one embodiment, when parallel processing unit 2002 is usedto perform graphics processing, scheduler 2010 can be configured todivide a processing workload into approximately equal sized tasks, tobetter enable distribution of graphics processing operations to multipleclusters 2014A-2014N of processing cluster array 2012. In at least oneembodiment, portions of processing cluster array 2012 can be configuredto perform different types of processing. For example, in at least oneembodiment, a first portion may be configured to perform vertex shadingand topology generation, a second portion may be configured to performtessellation and geometry shading, and a third portion may be configuredto perform pixel shading or other screen space operations, to produce arendered image for display. In at least one embodiment, intermediatedata produced by one or more of clusters 2014A-2014N may be stored inbuffers to allow intermediate data to be transmitted between clusters2014A-2014N for further processing.

In at least one embodiment, processing cluster array 2012 can receiveprocessing tasks to be executed via scheduler 2010, which receivescommands defining processing tasks from front end 2008. In at least oneembodiment, processing tasks can include indices of data to beprocessed, e.g., surface (patch) data, primitive data, vertex data,and/or pixel data, as well as state parameters and commands defining howdata is to be processed (e.g., what program is to be executed). In atleast one embodiment, scheduler 2010 may be configured to fetch indicescorresponding to tasks or may receive indices from front end 2008. In atleast one embodiment, front end 2008 can be configured to ensureprocessing cluster array 2012 is configured to a valid state before aworkload specified by incoming command buffers (e.g., batch-buffers,push buffers, etc.) is initiated.

In at least one embodiment, each of one or more instances of parallelprocessing unit 2002 can couple with a parallel processor memory 2022.In at least one embodiment, parallel processor memory 2022 can beaccessed via memory crossbar 2016, which can receive memory requestsfrom processing cluster array 2012 as well as I/O unit 2004. In at leastone embodiment, memory crossbar 2016 can access parallel processormemory 2022 via a memory interface 2018. In at least one embodiment,memory interface 2018 can include multiple partition units (e.g.,partition unit 2020A, partition unit 2020B, through partition unit2020N) that can each couple to a portion (e.g., memory unit) of parallelprocessor memory 2022. In at least one embodiment, a number of partitionunits 2020A-2020N is configured to be equal to a number of memory units,such that a first partition unit 2020A has a corresponding first memoryunit 2024A, a second partition unit 2020B has a corresponding memoryunit 2024B, and an N-th partition unit 2020N has a corresponding N-thmemory unit 2024N. In at least one embodiment, a number of partitionunits 2020A-2020N may not be equal to a number of memory units.

In at least one embodiment, memory units 2024A-2024N can include varioustypes of memory devices, including dynamic random access memory (DRAM)or graphics random access memory, such as synchronous graphics randomaccess memory (SGRAM), including graphics double data rate (GDDR)memory. In at least one embodiment, memory units 2024A-2024N may alsoinclude 3D stacked memory, including but not limited to high bandwidthmemory (HBM). In at least one embodiment, render targets, such as framebuffers or texture maps may be stored across memory units 2024A-2024N,allowing partition units 2020A-2020N to write portions of each rendertarget in parallel to efficiently use available bandwidth of parallelprocessor memory 2022. In at least one embodiment, a local instance ofparallel processor memory 2022 may be excluded in favor of a unifiedmemory design that utilizes system memory in conjunction with localcache memory.

In at least one embodiment, any one of clusters 2014A-2014N ofprocessing cluster array 2012 can process data that will be written toany of memory units 2024A-2024N within parallel processor memory 2022.In at least one embodiment, memory crossbar 2016 can be configured totransfer an output of each cluster 2014A-2014N to any partition unit2020A-2020N or to another cluster 2014A-2014N, which can performadditional processing operations on an output. In at least oneembodiment, each cluster 2014A-2014N can communicate with memoryinterface 2018 through memory crossbar 2016 to read from or write tovarious external memory devices. In at least one embodiment, memorycrossbar 2016 has a connection to memory interface 2018 to communicatewith I/O unit 2004, as well as a connection to a local instance ofparallel processor memory 2022, enabling processing units withindifferent processing clusters 2014A-2014N to communicate with systemmemory or other memory that is not local to parallel processing unit2002. In at least one embodiment, memory crossbar 2016 can use virtualchannels to separate traffic streams between clusters 2014A-2014N andpartition units 2020A-2020N.

In at least one embodiment, multiple instances of parallel processingunit 2002 can be provided on a single add-in card, or multiple add-incards can be interconnected. In at least one embodiment, differentinstances of parallel processing unit 2002 can be configured tointeroperate even if different instances have different numbers ofprocessing cores, different amounts of local parallel processor memory,and/or other configuration differences. For example, in at least oneembodiment, some instances of parallel processing unit 2002 can includehigher precision floating point units relative to other instances. In atleast one embodiment, systems incorporating one or more instances ofparallel processing unit 2002 or parallel processor 2000 can beimplemented in a variety of configurations and form factors, includingbut not limited to desktop, laptop, or handheld personal computers,servers, workstations, game consoles, and/or embedded systems.

FIG. 20B is a block diagram of a partition unit 2020 according to atleast one embodiment. In at least one embodiment, partition unit 2020 isan instance of one of partition units 2020A-2020N of FIG. 20A. In atleast one embodiment, partition unit 2020 includes an L2 cache 2021, aframe buffer interface 2025, and a ROP 2026 (raster operations unit). Inat least one embodiment, L2 cache 2021 is a read/write cache that isconfigured to perform load and store operations received from memorycrossbar 2016 and ROP 2026. In at least one embodiment, read misses andurgent write-back requests are output by L2 cache 2021 to frame bufferinterface 2025 for processing. In at least one embodiment, updates canalso be sent to a frame buffer via frame buffer interface 2025 forprocessing. In at least one embodiment, frame buffer interface 2025interfaces with one of memory units in parallel processor memory, suchas memory units 2024A-2024N of FIG. 20 (e.g., within parallel processormemory 2022).

In at least one embodiment, ROP 2026 is a processing unit that performsraster operations such as stencil, z test, blending, etc. In at leastone embodiment, ROP 2026 then outputs processed graphics data that isstored in graphics memory. In at least one embodiment, ROP 2026 includescompression logic to compress depth or color data that is written tomemory and decompress depth or color data that is read from memory. Inat least one embodiment, compression logic can be lossless compressionlogic that makes use of one or more of multiple compression algorithms.In at least one embodiment, a type of compression that is performed byROP 2026 can vary based on statistical characteristics of data to becompressed. For example, in at least one embodiment, delta colorcompression is performed on depth and color data on a per-tile basis.

In at least one embodiment, ROP 2026 is included within each processingcluster (e.g., cluster 2014A-2014N of FIG. 20A) instead of withinpartition unit 2020. In at least one embodiment, read and write requestsfor pixel data are transmitted over memory crossbar 2016 instead ofpixel fragment data. In at least one embodiment, processed graphics datamay be displayed on a display device, such as one of one or more displaydevice(s) 1910 of FIG. 19, routed for further processing by CPU(s) 1302,or routed for further processing by one of processing entities withinparallel processor 2000 of FIG. 20A.

FIG. 20C is a block diagram of a processing cluster 2014 within aparallel processing unit according to at least one embodiment. In atleast one embodiment, a processing cluster is an instance of one ofprocessing clusters 2014A-2014N of FIG. 20A. In at least one embodiment,processing cluster 2014 can be configured to execute many threads inparallel, where “thread” refers to an instance of a particular programexecuting on a particular set of input data. In at least one embodiment,single-instruction, multiple-data (SIMD) instruction issue techniquesare used to support parallel execution of a large number of threadswithout providing multiple independent instruction units. In at leastone embodiment, single-instruction, multiple-thread (SIMT) techniquesare used to support parallel execution of a large number of generallysynchronized threads, using a common instruction unit configured toissue instructions to a set of processing engines within each one ofprocessing clusters.

In at least one embodiment, operation of processing cluster 2014 can becontrolled via a pipeline manager 2032 that distributes processing tasksto SIMT parallel processors. In at least one embodiment, pipelinemanager 2032 receives instructions from scheduler 2010 of FIG. 20A andmanages execution of those instructions via a graphics multiprocessor2034 and/or a texture unit 2036. In at least one embodiment, graphicsmultiprocessor 2034 is an exemplary instance of a SIMT parallelprocessor. However, in at least one embodiment, various types of SIMTparallel processors of differing architectures may be included withinprocessing cluster 2014. In at least one embodiment, one or moreinstances of graphics multiprocessor 2034 can be included within aprocessing cluster 2014. In at least one embodiment, graphicsmultiprocessor 2034 can process data and a data crossbar 2040 can beused to distribute processed data to one of multiple possibledestinations, including other shader units. In at least one embodiment,pipeline manager 2032 can facilitate distribution of processed data byspecifying destinations for processed data to be distributed via datacrossbar 2040.

In at least one embodiment, each graphics multiprocessor 2034 withinprocessing cluster 2014 can include an identical set of functionalexecution logic (e.g., arithmetic logic units, load-store units, etc.).In at least one embodiment, functional execution logic can be configuredin a pipelined manner in which new instructions can be issued beforeprevious instructions are complete. In at least one embodiment,functional execution logic supports a variety of operations includinginteger and floating point arithmetic, comparison operations, Booleanoperations, bit-shifting, and computation of various algebraicfunctions. In at least one embodiment, same functional-unit hardware canbe leveraged to perform different operations and any combination offunctional units may be present.

In at least one embodiment, instructions transmitted to processingcluster 2014 constitute a thread. In at least one embodiment, a set ofthreads executing across a set of parallel processing engines is athread group. In at least one embodiment, a thread group executes acommon program on different input data. In at least one embodiment, eachthread within a thread group can be assigned to a different processingengine within a graphics multiprocessor 2034. In at least oneembodiment, a thread group may include fewer threads than a number ofprocessing engines within graphics multiprocessor 2034. In at least oneembodiment, when a thread group includes fewer threads than a number ofprocessing engines, one or more of processing engines may be idle duringcycles in which that thread group is being processed. In at least oneembodiment, a thread group may also include more threads than a numberof processing engines within graphics multiprocessor 2034. In at leastone embodiment, when a thread group includes more threads than number ofprocessing engines within graphics multiprocessor 2034, processing canbe performed over consecutive clock cycles. In at least one embodiment,multiple thread groups can be executed concurrently on a graphicsmultiprocessor 2034.

In at least one embodiment, graphics multiprocessor 2034 includes aninternal cache memory to perform load and store operations. In at leastone embodiment, graphics multiprocessor 2034 can forego an internalcache and use a cache memory (e.g., L1 cache 2048) within processingcluster 2014. In at least one embodiment, each graphics multiprocessor2034 also has access to L2 caches within partition units (e.g.,partition units 2020A-2020N of FIG. 20A) that are shared among allprocessing clusters 2014 and may be used to transfer data betweenthreads. In at least one embodiment, graphics multiprocessor 2034 mayalso access off-chip global memory, which can include one or more oflocal parallel processor memory and/or system memory. In at least oneembodiment, any memory external to parallel processing unit 2002 may beused as global memory. In at least one embodiment, processing cluster2014 includes multiple instances of graphics multiprocessor 2034 and canshare common instructions and data, which may be stored in L1 cache2048.

In at least one embodiment, each processing cluster 2014 may include anMMU 2045 (memory management unit) that is configured to map virtualaddresses into physical addresses. In at least one embodiment, one ormore instances of MMU 2045 may reside within memory interface 2018 ofFIG. 20A. In at least one embodiment, MMU 2045 includes a set of pagetable entries (PTEs) used to map a virtual address to a physical addressof a tile and optionally a cache line index. In at least one embodiment,MMU 2045 may include address translation lookaside buffers (TLB) orcaches that may reside within graphics multiprocessor 2034 or L1 2048cache or processing cluster 2014. In at least one embodiment, a physicaladdress is processed to distribute surface data access locally to allowfor efficient request interleaving among partition units. In at leastone embodiment, a cache line index may be used to determine whether arequest for a cache line is a hit or miss.

In at least one embodiment, a processing cluster 2014 may be configuredsuch that each graphics multiprocessor 2034 is coupled to a texture unit2036 for performing texture mapping operations, e.g., determiningtexture sample positions, reading texture data, and filtering texturedata. In at least one embodiment, texture data is read from an internaltexture L1 cache (not shown) or from an L1 cache within graphicsmultiprocessor 2034 and is fetched from an L2 cache, local parallelprocessor memory, or system memory, as needed. In at least oneembodiment, each graphics multiprocessor 2034 outputs processed tasks todata crossbar 2040 to provide processed task to another processingcluster 2014 for further processing or to store processed task in an L2cache, local parallel processor memory, or system memory via memorycrossbar 2016. In at least one embodiment, a preROP 2042 (pre-rasteroperations unit) is configured to receive data from graphicsmultiprocessor 2034, and direct data to ROP units, which may be locatedwith partition units as described herein (e.g., partition units2020A-2020N of FIG. 20A). In at least one embodiment, preROP 2042 unitcan perform optimizations for color blending, organizing pixel colordata, and performing address translations.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used in graphicsprocessing cluster 2014 for inferencing or predicting operations based,at least in part, on weight parameters calculated using neural networktraining operations, neural network functions and/or architectures, orneural network use cases described herein.

FIG. 20D shows a graphics multiprocessor 2034 according to at least oneembodiment. In at least one embodiment, graphics multiprocessor 2034couples with pipeline manager 2032 of processing cluster 2014. In atleast one embodiment, graphics multiprocessor 2034 has an executionpipeline including but not limited to an instruction cache 2052, aninstruction unit 2054, an address mapping unit 2056, a register file2058, one or more general purpose graphics processing unit (GPGPU) cores2062, and one or more load/store units 2066. In at least one embodiment,GPGPU cores 2062 and load/store units 2066 are coupled with cache memory2072 and shared memory 2070 via a memory and cache interconnect 2068.

In at least one embodiment, instruction cache 2052 receives a stream ofinstructions to execute from pipeline manager 2032. In at least oneembodiment, instructions are cached in instruction cache 2052 anddispatched for execution by an instruction unit 2054. In at least oneembodiment, instruction unit 2054 can dispatch instructions as threadgroups (e.g., warps), with each thread of thread group assigned to adifferent execution unit within GPGPU cores 2062. In at least oneembodiment, an instruction can access any of a local, shared, or globaladdress space by specifying an address within a unified address space.In at least one embodiment, address mapping unit 2056 can be used totranslate addresses in a unified address space into a distinct memoryaddress that can be accessed by load/store units 2066.

In at least one embodiment, register file 2058 provides a set ofregisters for functional units of graphics multiprocessor 2034. In atleast one embodiment, register file 2058 provides temporary storage foroperands connected to data paths of functional units (e.g., GPGPU cores2062, load/store units 2066) of graphics multiprocessor 2034. In atleast one embodiment, register file 2058 is divided between each offunctional units such that each functional unit is allocated a dedicatedportion of register file 2058. In at least one embodiment, register file2058 is divided between different warps being executed by graphicsmultiprocessor 2034.

In at least one embodiment, GPGPU cores 2062 can each include floatingpoint units (FPUs) and/or integer arithmetic logic units (ALUs) that areused to execute instructions of graphics multiprocessor 2034. In atleast one embodiment, GPGPU cores 2062 can be similar in architecture orcan differ in architecture. In at least one embodiment, a first portionof GPGPU cores 2062 include a single precision FPU and an integer ALUwhile a second portion of GPGPU cores include a double precision FPU. Inat least one embodiment, FPUs can implement IEEE 754-2008 standardfloating point arithmetic or enable variable precision floating pointarithmetic. In at least one embodiment, graphics multiprocessor 2034 canadditionally include one or more fixed function or special functionunits to perform specific functions such as copy rectangle or pixelblending operations. In at least one embodiment, one or more of GPGPUcores 2062 can also include fixed or special function logic.

In at least one embodiment, GPGPU cores 2062 include SIMD logic capableof performing a single instruction on multiple sets of data. In at leastone embodiment, GPGPU cores 2062 can physically execute SIMD4, SIMD8,and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32instructions. In at least one embodiment, SIMD instructions for GPGPUcores can be generated at compile time by a shader compiler orautomatically generated when executing programs written and compiled forsingle program multiple data (SPMD) or SIMT architectures. In at leastone embodiment, multiple threads of a program configured for an SIMTexecution model can executed via a single SIMD instruction. For example,in at least one embodiment, eight SIMT threads that perform same orsimilar operations can be executed in parallel via a single SIMD8 logicunit.

In at least one embodiment, memory and cache interconnect 2068 is aninterconnect network that connects each functional unit of graphicsmultiprocessor 2034 to register file 2058 and to shared memory 2070. Inat least one embodiment, memory and cache interconnect 2068 is acrossbar interconnect that allows load/store unit 2066 to implement loadand store operations between shared memory 2070 and register file 2058.In at least one embodiment, register file 2058 can operate at a samefrequency as GPGPU cores 2062, thus data transfer between GPGPU cores2062 and register file 2058 can have very low latency. In at least oneembodiment, shared memory 2070 can be used to enable communicationbetween threads that execute on functional units within graphicsmultiprocessor 2034. In at least one embodiment, cache memory 2072 canbe used as a data cache for example, to cache texture data communicatedbetween functional units and texture unit 2036. In at least oneembodiment, shared memory 2070 can also be used as a program managedcache. In at least one embodiment, threads executing on GPGPU cores 2062can programmatically store data within shared memory in addition toautomatically cached data that is stored within cache memory 2072.

In at least one embodiment, a parallel processor or GPGPU as describedherein is communicatively coupled to host/processor cores to accelerategraphics operations, machine-learning operations, pattern analysisoperations, and various general purpose GPU (GPGPU) functions. In atleast one embodiment, a GPU may be communicatively coupled to hostprocessor/cores over a bus or other interconnect (e.g., a high-speedinterconnect such as PCIe or NVLink). In at least one embodiment, a GPUmay be integrated on a package or chip as cores and communicativelycoupled to cores over an internal processor bus/interconnect internal toa package or chip. In at least one embodiment, regardless a manner inwhich a GPU is connected, processor cores may allocate work to such GPUin a form of sequences of commands/instructions contained in a workdescriptor. In at least one embodiment, that GPU then uses dedicatedcircuitry/logic for efficiently processing these commands/instructions.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used in graphicsmultiprocessor 2034 for inferencing or predicting operations based, atleast in part, on weight parameters calculated using neural networktraining operations, neural network functions and/or architectures, orneural network use cases described herein.

FIG. 21 illustrates a multi-GPU computing system 2100, according to atleast one embodiment. In at least one embodiment, multi-GPU computingsystem 2100 can include a processor 2102 coupled to multiple generalpurpose graphics processing units (GPGPUs) 2106A-D via a host interfaceswitch 2104. In at least one embodiment, host interface switch 2104 is aPCI express switch device that couples processor 2102 to a PCI expressbus over which processor 2102 can communicate with GPGPUs 2106A-D. In atleast one embodiment, GPGPUs 2106A-D can interconnect via a set ofhigh-speed point-to-point GPU-to-GPU links 2116. In at least oneembodiment, GPU-to-GPU links 2116 connect to each of GPGPUs 2106A-D viaa dedicated GPU link. In at least one embodiment, P2P GPU links 2116enable direct communication between each of GPGPUs 2106A-D withoutrequiring communication over host interface bus 2104 to which processor2102 is connected. In at least one embodiment, with GPU-to-GPU trafficdirected to P2P GPU links 2116, host interface bus 2104 remainsavailable for system memory access or to communicate with otherinstances of multi-GPU computing system 2100, for example, via one ormore network devices. While in at least one embodiment GPGPUs 2106A-Dconnect to processor 2102 via host interface switch 2104, in at leastone embodiment processor 2102 includes direct support for P2P GPU links2116 and can connect directly to GPGPUs 2106A-D.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used in multi-GPUcomputing system 1500 for inferencing or predicting operations based, atleast in part, on weight parameters calculated using neural networktraining operations, neural network functions and/or architectures, orneural network use cases described herein.

FIG. 22 is a block diagram of a graphics processor 2200, according to atleast one embodiment. In at least one embodiment, graphics processor2200 includes a ring interconnect 2202, a pipeline front-end 2204, amedia engine 2237, and graphics cores 2280A-2280N. In at least oneembodiment, ring interconnect 2202 couples graphics processor 2200 toother processing units, including other graphics processors or one ormore general-purpose processor cores. In at least one embodiment,graphics processor 2200 is one of many processors integrated within amulti-core processing system.

In at least one embodiment, graphics processor 2200 receives batches ofcommands via ring interconnect 2202. In at least one embodiment,incoming commands are interpreted by a command streamer 2203 in pipelinefront-end 2204. In at least one embodiment, graphics processor 2200includes scalable execution logic to perform 3D geometry processing andmedia processing via graphics core(s) 2280A-2280N. In at least oneembodiment, for 3D geometry processing commands, command streamer 2203supplies commands to geometry pipeline 2236. In at least one embodiment,for at least some media processing commands, command streamer 2203supplies commands to a video front end 2234, which couples with mediaengine 2237. In at least one embodiment, media engine 2237 includes aVideo Quality Engine (VQE) 2230 for video and image post-processing anda multi-format encode/decode (MFX) 2233 engine to providehardware-accelerated media data encoding and decoding. In at least oneembodiment, geometry pipeline 2236 and media engine 2237 each generateexecution threads for thread execution resources provided by at leastone graphics core 2280.

In at least one embodiment, graphics processor 2200 includes scalablethread execution resources featuring graphics cores 2280A-2280N (whichcan be modular and are sometimes referred to as core slices), eachhaving multiple sub-cores 2250A-50N, 2260A-2260N (sometimes referred toas core sub-slices). In at least one embodiment, graphics processor 2200can have any number of graphics cores 2280A. In at least one embodiment,graphics processor 2200 includes a graphics core 2280A having at least afirst sub-core 2250A and a second sub-core 2260A. In at least oneembodiment, graphics processor 2200 is a low power processor with asingle sub-core (e.g., 2250A). In at least one embodiment, graphicsprocessor 2200 includes multiple graphics cores 2280A-2280N, eachincluding a set of first sub-cores 2250A-2250N and a set of secondsub-cores 2260A-2260N. In at least one embodiment, each sub-core infirst sub-cores 2250A-2250N includes at least a first set of executionunits 2252A-2252N and media/texture samplers 2254A-2254N. In at leastone embodiment, each sub-core in second sub-cores 2260A-2260N includesat least a second set of execution units 2262A-2262N and samplers2264A-2264N. In at least one embodiment, each sub-core 2250A-2250N,2260A-2260N shares a set of shared resources 2270A-2270N. In at leastone embodiment, shared resources include shared cache memory and pixeloperation logic.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, inference and/or training logic 115 may be used in graphicsprocessor 2200 for inferencing or predicting operations based, at leastin part, on weight parameters calculated using neural network trainingoperations, neural network functions and/or architectures, or neuralnetwork use cases described herein.

FIG. 23 is a block diagram illustrating micro-architecture for aprocessor 2300 that may include logic circuits to perform instructions,according to at least one embodiment. In at least one embodiment,processor 2300 may perform instructions, including x86 instructions, ARMinstructions, specialized instructions for application-specificintegrated circuits (ASICs), etc. In at least one embodiment, processor2300 may include registers to store packed data, such as 64-bit wideMMX™ registers in microprocessors enabled with MMX technology from IntelCorporation of Santa Clara, Calif In at least one embodiment, MMXregisters, available in both integer and floating point forms, mayoperate with packed data elements that accompany single instruction,multiple data (“SIND”) and streaming SIMD extensions (“SSE”)instructions. In at least one embodiment, 128-bit wide XMM registersrelating to SSE2, SSE3, SSE4, AVX, or beyond (referred to generically as“SSEx”) technology may hold such packed data operands. In at least oneembodiment, processor 2300 may perform instructions to acceleratemachine learning or deep learning algorithms, training, or inferencing.

In at least one embodiment, processor 2300 includes an in-order frontend (“front end”) 2301 to fetch instructions to be executed and prepareinstructions to be used later in a processor pipeline. In at least oneembodiment, front end 2301 may include several units. In at least oneembodiment, an instruction prefetcher 2326 fetches instructions frommemory and feeds instructions to an instruction decoder 2328 which inturn decodes or interprets instructions. For example, in at least oneembodiment, instruction decoder 2328 decodes a received instruction intoone or more operations called “micro-instructions” or “micro-operations”(also called “micro ops” or “uops”) that a machine may execute. In atleast one embodiment, instruction decoder 2328 parses an instructioninto an opcode and corresponding data and control fields that may beused by micro-architecture to perform operations in accordance with atleast one embodiment. In at least one embodiment, a trace cache 2330 mayassemble decoded uops into program ordered sequences or traces in a uopqueue 2334 for execution. In at least one embodiment, when trace cache2330 encounters a complex instruction, a microcode ROM 2332 providesuops needed to complete an operation.

In at least one embodiment, some instructions may be converted into asingle micro-op, whereas others need several micro-ops to complete fulloperation. In at least one embodiment, if more than four micro-ops areneeded to complete an instruction, instruction decoder 2328 may accessmicrocode ROM 2332 to perform that instruction. In at least oneembodiment, an instruction may be decoded into a small number ofmicro-ops for processing at instruction decoder 2328. In at least oneembodiment, an instruction may be stored within microcode ROM 2332should a number of micro-ops be needed to accomplish such operation. Inat least one embodiment, trace cache 2330 refers to an entry pointprogrammable logic array (“PLA”) to determine a correctmicro-instruction pointer for reading microcode sequences to completeone or more instructions from microcode ROM 2332 in accordance with atleast one embodiment. In at least one embodiment, after microcode ROM2332 finishes sequencing micro-ops for an instruction, front end 2301 ofa machine may resume fetching micro-ops from trace cache 2330.

In at least one embodiment, out-of-order execution engine (“out of orderengine”) 2303 may prepare instructions for execution. In at least oneembodiment, out-of-order execution logic has a number of buffers tosmooth out and re-order flow of instructions to optimize performance asthey go down a pipeline and get scheduled for execution. In at least oneembodiment, out-of-order execution engine 2303 includes, withoutlimitation, an allocator/register renamer 2340, a memory uop queue 2342,an integer/floating point uop queue 2344, a memory scheduler 2346, afast scheduler 2302, a slow/general floating point scheduler(“slow/general FP scheduler”) 2304, and a simple floating pointscheduler (“simple FP scheduler”) 2306. In at least one embodiment, fastschedule 2302, slow/general floating point scheduler 2304, and simplefloating point scheduler 2306 are also collectively referred to hereinas “uop schedulers 2302, 2304, 2306.” In at least one embodiment,allocator/register renamer 2340 allocates machine buffers and resourcesthat each uop needs in order to execute. In at least one embodiment,allocator/register renamer 2340 renames logic registers onto entries ina register file. In at least one embodiment, allocator/register renamer2340 also allocates an entry for each uop in one of two uop queues,memory uop queue 2342 for memory operations and integer/floating pointuop queue 2344 for non-memory operations, in front of memory scheduler2346 and uop schedulers 2302, 2304, 2306. In at least one embodiment,uop schedulers 2302, 2304, 2306, determine when a uop is ready toexecute based on readiness of their dependent input register operandsources and availability of execution resources uops need to completetheir operation. In at least one embodiment, fast scheduler 2302 mayschedule on each half of a main clock cycle while slow/general floatingpoint scheduler 2304 and simple floating point scheduler 2306 mayschedule once per main processor clock cycle. In at least oneembodiment, uop schedulers 2302, 2304, 2306 arbitrate for dispatch portsto schedule uops for execution.

In at least one embodiment, execution block 2311 includes, withoutlimitation, an integer register file/bypass network 2308, a floatingpoint register file/bypass network (“FP register file/bypass network”)2310, address generation units (“AGUs”) 2312 and 2314, fast ArithmeticLogic Units (ALUs) (“fast ALUs”) 2316 and 2318, a slow Arithmetic LogicUnit (“slow ALU”) 2320, a floating point ALU (“FP”) 2322, and a floatingpoint move unit (“FP move”) 2324. In at least one embodiment, integerregister file/bypass network 2308 and floating point registerfile/bypass network 2310 are also referred to herein as “register files2308, 2310.” In at least one embodiment, AGUSs 2312 and 2314, fast ALUs2316 and 2318, slow ALU 2320, floating point ALU 2322, and floatingpoint move unit 2324 are also referred to herein as “execution units2312, 2314, 2316, 2318, 2320, 2322, and 2324.” In at least oneembodiment, execution block 2311 may include, without limitation, anynumber (including zero) and type of register files, bypass networks,address generation units, and execution units, in any combination.

In at least one embodiment, register networks 2308, 2310 may be arrangedbetween uop schedulers 2302, 2304, 2306, and execution units 2312, 2314,2316, 2318, 2320, 2322, and 2324. In at least one embodiment, integerregister file/bypass network 2308 performs integer operations. In atleast one embodiment, floating point register file/bypass network 2310performs floating point operations. In at least one embodiment, each ofregister networks 2308, 2310 may include, without limitation, a bypassnetwork that may bypass or forward just completed results that have notyet been written into a register file to new dependent uops. In at leastone embodiment, register networks 2308, 2310 may communicate data witheach other. In at least one embodiment, integer register file/bypassnetwork 2308 may include, without limitation, two separate registerfiles, one register file for a low-order thirty-two bits of data and asecond register file for a high order thirty-two bits of data. In atleast one embodiment, floating point register file/bypass network 2310may include, without limitation, 128-bit wide entries because floatingpoint instructions typically have operands from 64 to 128 bits in width.

In at least one embodiment, execution units 2312, 2314, 2316, 2318,2320, 2322, 2324 may execute instructions. In at least one embodiment,register networks 2308, 2310 store integer and floating point dataoperand values that micro-instructions need to execute. In at least oneembodiment, processor 2300 may include, without limitation, any numberand combination of execution units 2312, 2314, 2316, 2318, 2320, 2322,2324. In at least one embodiment, floating point ALU 2322 and floatingpoint move unit 2324, may execute floating point, MMX, SIMD, AVX andSSE, or other operations, including specialized machine learninginstructions. In at least one embodiment, floating point ALU 2322 mayinclude, without limitation, a 64-bit by 64-bit floating point dividerto execute divide, square root, and remainder micro ops. In at least oneembodiment, instructions involving a floating point value may be handledwith floating point hardware. In at least one embodiment, ALU operationsmay be passed to fast ALUs 2316, 2318. In at least one embodiment, fastALUS 2316, 2318 may execute fast operations with an effective latency ofhalf a clock cycle. In at least one embodiment, most complex integeroperations go to slow ALU 2320 as slow ALU 2320 may include, withoutlimitation, integer execution hardware for long-latency type ofoperations, such as a multiplier, shifts, flag logic, and branchprocessing. In at least one embodiment, memory load/store operations maybe executed by AGUs 2312, 2314. In at least one embodiment, fast ALU2316, fast ALU 2318, and slow ALU 2320 may perform integer operations on64-bit data operands. In at least one embodiment, fast ALU 2316, fastALU 2318, and slow ALU 2320 may be implemented to support a variety ofdata bit sizes including sixteen, thirty-two, 128, 256, etc. In at leastone embodiment, floating point ALU 2322 and floating point move unit2324 may be implemented to support a range of operands having bits ofvarious widths, such as 128-bit wide packed data operands in conjunctionwith SIMD and multimedia instructions.

In at least one embodiment, uop schedulers 2302, 2304, 2306 dispatchdependent operations before a parent load has finished executing. In atleast one embodiment, as uops may be speculatively scheduled andexecuted in processor 2300, processor 2300 may also include logic tohandle memory misses. In at least one embodiment, if a data load missesin a data cache, there may be dependent operations in flight in apipeline that have left a scheduler with temporarily incorrect data. Inat least one embodiment, a replay mechanism tracks and re-executesinstructions that use incorrect data. In at least one embodiment,dependent operations might need to be replayed and independent ones maybe allowed to complete. In at least one embodiment, schedulers and areplay mechanism of at least one embodiment of a processor may also bedesigned to catch instruction sequences for text string comparisonoperations.

In at least one embodiment, “registers” may refer to on-board processorstorage locations that may be used as part of instructions to identifyoperands. In at least one embodiment, registers may be those that may beusable from outside of a processor (from a programmer's perspective). Inat least one embodiment, registers might not be limited to a particulartype of circuit. Rather, in at least one embodiment, a register maystore data, provide data, and perform functions described herein. In atleast one embodiment, registers described herein may be implemented bycircuitry within a processor using any number of different techniques,such as dedicated physical registers, dynamically allocated physicalregisters using register renaming, combinations of dedicated anddynamically allocated physical registers, etc. In at least oneembodiment, integer registers store 32-bit integer data. A register fileof at least one embodiment also contains eight multimedia SIND registersfor packed data.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment portions or all of inference and/or training logic 115 may beincorporated into execution block 2311 and other memory or registersshown or not shown. For example, in at least one embodiment, trainingand/or inferencing techniques described herein may use one or more ofALUs illustrated in execution block 2311. Moreover, weight parametersmay be stored in on-chip or off-chip memory and/or registers (shown ornot shown) that configure ALUs of execution block 2311 to perform one ormore machine learning algorithms, neural network architectures, usecases, or training techniques described herein.

FIG. 24 illustrates a deep learning application processor 2400,according to at least one embodiment. In at least one embodiment, deeplearning application processor 2400 uses instructions that, if executedby deep learning application processor 2400, cause deep learningapplication processor 2400 to perform some or all of processes andtechniques described throughout this disclosure. In at least oneembodiment, deep learning application processor 2400 is anapplication-specific integrated circuit (ASIC). In at least oneembodiment, application processor 2400 performs matrix multiplyoperations either “hard-wired” into hardware as a result of performingone or more instructions or both. In at least one embodiment, deeplearning application processor 2400 includes, without limitation,processing clusters 2410(1)-2410(12), Inter-Chip Links (“ICLs”)2420(1)-2420(12), Inter-Chip Controllers (“ICCs”) 2430(1)-2430(2),high-bandwidth memory second generation (“HBM2”) 2440(1)-2440(4), memorycontrollers (“Mem Ctrlrs”) 2442(1)-2442(4), high bandwidth memoryphysical layer (“HBM PHY”) 2444(1)-2444(4), a management-controllercentral processing unit (“management-controller CPU”) 2450, a SerialPeripheral Interface, Inter-Integrated Circuit, and General PurposeInput/Output block (“SPI, I2C, GPIO”) 2460, a peripheral componentinterconnect express controller and direct memory access block (“PCIeController and DMA”) 2470, and a sixteen-lane peripheral componentinterconnect express port (“PCI Express x 16”) 2480.

In at least one embodiment, processing clusters 2410 may perform deeplearning operations, including inference or prediction operations basedon weight parameters calculated one or more training techniques,including those described herein. In at least one embodiment, eachprocessing cluster 2410 may include, without limitation, any number andtype of processors. In at least one embodiment, deep learningapplication processor 2400 may include any number and type of processingclusters. In at least one embodiment, Inter-Chip Links 2420 arebi-directional. In at least one embodiment, Inter-Chip Links 2420 andInter-Chip Controllers 2430 enable multiple deep learning applicationprocessors 2400 to exchange information, including activationinformation resulting from performing one or more machine learningalgorithms embodied in one or more neural networks. In at least oneembodiment, deep learning application processor 2400 may include anynumber (including zero) and type of ICLs 2420 and ICCs 2430.

In at least one embodiment, HBM2s 2440 provide a total of 32 Gigabytes(GB) of memory. In at least one embodiment, HBM2 2440(i) is associatedwith both memory controller 2442(i) and HBM PHY 2444(i) where “i” is anarbitrary integer. In at least one embodiment, any number of HBM2s 2440may provide any type and total amount of high bandwidth memory and maybe associated with any number (including zero) and type of memorycontrollers 2442 and HBM PHYs 2444. In at least one embodiment, SPI,I2C, GPIO 2460, PCIe Controller and DMA 2470, and/or PCIe 2480 may bereplaced with any number and type of blocks that enable any number andtype of communication standards in any technically feasible fashion.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, deep learning application processor is used to train amachine learning model, such as a neural network, to predict or inferinformation provided to deep learning application processor 2400. In atleast one embodiment, deep learning application processor 2400 is usedto infer or predict information based on a trained machine learningmodel (e.g., neural network) that has been trained by another processoror system or by deep learning application processor 2400. In at leastone embodiment, processor 2400 may be used to perform one or more neuralnetwork use cases described herein.

FIG. 25 is a block diagram of a neuromorphic processor 2500, accordingto at least one embodiment. In at least one embodiment, neuromorphicprocessor 2500 may receive one or more inputs from sources external toneuromorphic processor 2500. In at least one embodiment, these inputsmay be transmitted to one or more neurons 2502 within neuromorphicprocessor 2500. In at least one embodiment, neurons 2502 and componentsthereof may be implemented using circuitry or logic, including one ormore arithmetic logic units (ALUs). In at least one embodiment,neuromorphic processor 2500 may include, without limitation, thousandsor millions of instances of neurons 2502, but any suitable number ofneurons 2502 may be used. In at least one embodiment, each instance ofneuron 2502 may include a neuron input 2504 and a neuron output 2506. Inat least one embodiment, neurons 2502 may generate outputs that may betransmitted to inputs of other instances of neurons 2502. For example,in at least one embodiment, neuron inputs 2504 and neuron outputs 2506may be interconnected via synapses 2508.

In at least one embodiment, neurons 2502 and synapses 2508 may beinterconnected such that neuromorphic processor 2500 operates to processor analyze information received by neuromorphic processor 2500. In atleast one embodiment, neurons 2502 may transmit an output pulse (or“fire” or “spike”) when inputs received through neuron input 2504 exceeda threshold. In at least one embodiment, neurons 2502 may sum orintegrate signals received at neuron inputs 2504. For example, in atleast one embodiment, neurons 2502 may be implemented as leakyintegrate-and-fire neurons, wherein if a sum (referred to as a “membranepotential”) exceeds a threshold value, neuron 2502 may generate anoutput (or “fire”) using a transfer function such as a sigmoid orthreshold function. In at least one embodiment, a leakyintegrate-and-fire neuron may sum signals received at neuron inputs 2504into a membrane potential and may also apply a decay factor (or leak) toreduce a membrane potential. In at least one embodiment, a leakyintegrate-and-fire neuron may fire if multiple input signals arereceived at neuron inputs 2504 rapidly enough to exceed a thresholdvalue (i.e., before a membrane potential decays too low to fire). In atleast one embodiment, neurons 2502 may be implemented using circuits orlogic that receive inputs, integrate inputs into a membrane potential,and decay a membrane potential. In at least one embodiment, inputs maybe averaged, or any other suitable transfer function may be used.Furthermore, in at least one embodiment, neurons 2502 may include,without limitation, comparator circuits or logic that generate an outputspike at neuron output 2506 when result of applying a transfer functionto neuron input 2504 exceeds a threshold. In at least one embodiment,once neuron 2502 fires, it may disregard previously received inputinformation by, for example, resetting a membrane potential to 0 oranother suitable default value. In at least one embodiment, oncemembrane potential is reset to 0, neuron 2502 may resume normaloperation after a suitable period of time (or refractory period).

In at least one embodiment, neurons 2502 may be interconnected throughsynapses 2508. In at least one embodiment, synapses 2508 may operate totransmit signals from an output of a first neuron 2502 to an input of asecond neuron 2502. In at least one embodiment, neurons 2502 maytransmit information over more than one instance of synapse 2508. In atleast one embodiment, one or more instances of neuron output 2506 may beconnected, via an instance of synapse 2508, to an instance of neuroninput 2504 in same neuron 2502. In at least one embodiment, an instanceof neuron 2502 generating an output to be transmitted over an instanceof synapse 2508 may be referred to as a “pre-synaptic neuron” withrespect to that instance of synapse 2508. In at least one embodiment, aninstance of neuron 2502 receiving an input transmitted over an instanceof synapse 2508 may be referred to as a “post-synaptic neuron” withrespect to that instance of synapse 2508. Because an instance of neuron2502 may receive inputs from one or more instances of synapse 2508, andmay also transmit outputs over one or more instances of synapse 2508, asingle instance of neuron 2502 may therefore be both a “pre-synapticneuron” and “post-synaptic neuron,” with respect to various instances ofsynapses 2508, in at least one embodiment.

In at least one embodiment, neurons 2502 may be organized into one ormore layers. In at least one embodiment, each instance of neuron 2502may have one neuron output 2506 that may fan out through one or moresynapses 2508 to one or more neuron inputs 2504. In at least oneembodiment, neuron outputs 2506 of neurons 2502 in a first layer 2510may be connected to neuron inputs 2504 of neurons 2502 in a second layer2512. In at least one embodiment, layer 2510 may be referred to as a“feed-forward layer.” In at least one embodiment, each instance ofneuron 2502 in an instance of first layer 2510 may fan out to eachinstance of neuron 2502 in second layer 2512. In at least oneembodiment, first layer 2510 may be referred to as a “fully connectedfeed-forward layer.” In at least one embodiment, each instance of neuron2502 in an instance of second layer 2512 may fan out to fewer than allinstances of neuron 2502 in a third layer 2514. In at least oneembodiment, second layer 2512 may be referred to as a “sparselyconnected feed-forward layer.” In at least one embodiment, neurons 2502in second layer 2512 may fan out to neurons 2502 in multiple otherlayers, including to neurons 2502 also in second layer 2512. In at leastone embodiment, second layer 2512 may be referred to as a “recurrentlayer.” In at least one embodiment, neuromorphic processor 2500 mayinclude, without limitation, any suitable combination of recurrentlayers and feed-forward layers, including, without limitation, bothsparsely connected feed-forward layers and fully connected feed-forwardlayers.

In at least one embodiment, neuromorphic processor 2500 may include,without limitation, a reconfigurable interconnect architecture ordedicated hard-wired interconnects to connect synapse 2508 to neurons2502. In at least one embodiment, neuromorphic processor 2500 mayinclude, without limitation, circuitry or logic that allows synapses tobe allocated to different neurons 2502 as needed based on neural networktopology and neuron fan-in/out. For example, in at least one embodiment,synapses 2508 may be connected to neurons 2502 using an interconnectfabric, such as network-on-chip, or with dedicated connections. In atleast one embodiment, synapse interconnections and components thereofmay be implemented using circuitry or logic.

FIG. 26 is a block diagram of a processing system, according to at leastone embodiment. In at least one embodiment, system 2600 includes one ormore processors 2602 and one or more graphics processors 2608, and maybe a single processor desktop system, a multiprocessor workstationsystem, or a server system having a large number of processors 2602 orprocessor cores 2607. In at least one embodiment, system 2600 is aprocessing platform incorporated within a system-on-a-chip (SoC)integrated circuit for use in mobile, handheld, or embedded devices.

In at least one embodiment, system 2600 can include, or be incorporatedwithin a server-based gaming platform, a game console, including a gameand media console, a mobile gaming console, a handheld game console, oran online game console. In at least one embodiment, system 2600 is amobile phone, a smart phone, a tablet computing device or a mobileInternet device. In at least one embodiment, processing system 2600 canalso include, couple with, or be integrated within a wearable device,such as a smart watch wearable device, a smart eyewear device, anaugmented reality device, or a virtual reality device. In at least oneembodiment, processing system 2600 is a television or set top box devicehaving one or more processors 2602 and a graphical interface generatedby one or more graphics processors 2608.

In at least one embodiment, one or more processors 2602 each include oneor more processor cores 2607 to process instructions which, whenexecuted, perform operations for system and user software. In at leastone embodiment, each of one or more processor cores 2607 is configuredto process a specific instruction sequence 2609. In at least oneembodiment, instruction sequence 2609 may facilitate Complex InstructionSet Computing (CISC), Reduced Instruction Set Computing (RISC), orcomputing via a Very Long Instruction Word (VLIW). In at least oneembodiment, processor cores 2607 may each process a differentinstruction sequence 2609, which may include instructions to facilitateemulation of other instruction sequences. In at least one embodiment,processor core 2607 may also include other processing devices, such aDigital Signal Processor (DSP).

In at least one embodiment, processor 2602 includes a cache memory 2604.In at least one embodiment, processor 2602 can have a single internalcache or multiple levels of internal cache. In at least one embodiment,cache memory is shared among various components of processor 2602. In atleast one embodiment, processor 2602 also uses an external cache (e.g.,a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which maybe shared among processor cores 2607 using known cache coherencytechniques. In at least one embodiment, a register file 2606 isadditionally included in processor 2602, which may include differenttypes of registers for storing different types of data (e.g., integerregisters, floating point registers, status registers, and aninstruction pointer register). In at least one embodiment, register file2606 may include general-purpose registers or other registers.

In at least one embodiment, one or more processor(s) 2602 are coupledwith one or more interface bus(es) 2610 to transmit communicationsignals such as address, data, or control signals between processor 2602and other components in system 2600. In at least one embodiment,interface bus 2610 can be a processor bus, such as a version of a DirectMedia Interface (DMI) bus. In at least one embodiment, interface bus2610 is not limited to a DMI bus, and may include one or more PeripheralComponent Interconnect buses (e.g., PCI, PCI Express), memory busses, orother types of interface busses. In at least one embodiment processor(s)2602 include an integrated memory controller 2616 and a platformcontroller hub 2630. In at least one embodiment, memory controller 2616facilitates communication between a memory device and other componentsof system 2600, while platform controller hub (PCH) 2630 providesconnections to I/O devices via a local I/O bus.

In at least one embodiment, a memory device 2620 can be a dynamic randomaccess memory (DRAM) device, a static random access memory (SRAM)device, flash memory device, phase-change memory device, or some othermemory device having suitable performance to serve as process memory. Inat least one embodiment, memory device 2620 can operate as system memoryfor system 2600, to store data 2622 and instructions 2621 for use whenone or more processors 2602 executes an application or process. In atleast one embodiment, memory controller 2616 also couples with anoptional external graphics processor 2612, which may communicate withone or more graphics processors 2608 in processors 2602 to performgraphics and media operations. In at least one embodiment, a displaydevice 2611 can connect to processor(s) 2602. In at least oneembodiment, display device 2611 can include one or more of an internaldisplay device, as in a mobile electronic device or a laptop device, oran external display device attached via a display interface (e.g.,DisplayPort, etc.). In at least one embodiment, display device 2611 caninclude a head mounted display (HMD) such as a stereoscopic displaydevice for use in virtual reality (VR) applications or augmented reality(AR) applications.

In at least one embodiment, platform controller hub 2630 enablesperipherals to connect to memory device 2620 and processor 2602 via ahigh-speed I/O bus. In at least one embodiment, I/O peripherals include,but are not limited to, an audio controller 2646, a network controller2634, a firmware interface 2628, a wireless transceiver 2626, touchsensors 2625, a data storage device 2624 (e.g., hard disk drive, flashmemory, etc.). In at least one embodiment, data storage device 2624 canconnect via a storage interface (e.g., SATA) or via a peripheral bus,such as a Peripheral Component Interconnect bus (e.g., PCI, PCIExpress). In at least one embodiment, touch sensors 2625 can includetouch screen sensors, pressure sensors, or fingerprint sensors. In atleast one embodiment, wireless transceiver 2626 can be a Wi-Fitransceiver, a Bluetooth transceiver, or a mobile network transceiversuch as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at leastone embodiment, firmware interface 2628 enables communication withsystem firmware, and can be, for example, a unified extensible firmwareinterface (UEFI). In at least one embodiment, network controller 2634can enable a network connection to a wired network. In at least oneembodiment, a high-performance network controller (not shown) coupleswith interface bus 2610. In at least one embodiment, audio controller2646 is a multi-channel high definition audio controller. In at leastone embodiment, system 2600 includes an optional legacy I/O controller2640 for coupling legacy (e.g., Personal System 2 (PS/2)) devices tosystem 2600. In at least one embodiment, platform controller hub 2630can also connect to one or more Universal Serial Bus (USB) controllers2642 connect input devices, such as keyboard and mouse 2643combinations, a camera 2644, or other USB input devices.

In at least one embodiment, an instance of memory controller 2616 andplatform controller hub 2630 may be integrated into a discreet externalgraphics processor, such as external graphics processor 2612. In atleast one embodiment, platform controller hub 2630 and/or memorycontroller 2616 may be external to one or more processor(s) 2602. Forexample, in at least one embodiment, system 2600 can include an externalmemory controller 2616 and platform controller hub 2630, which may beconfigured as a memory controller hub and peripheral controller hubwithin a system chipset that is in communication with processor(s) 2602.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment portions or all of inference and/or training logic 115 may beincorporated into system 2600. For example, in at least one embodiment,training and/or inferencing techniques described herein may use one ormore of ALUs embodied in a 3D pipeline. Moreover, in at least oneembodiment, inferencing and/or training operations described herein maybe done using logic other than logic illustrated in FIG. 1A or 1B. In atleast one embodiment, weight parameters may be stored in on-chip oroff-chip memory and/or registers (shown or not shown) that configureALUs of graphics processor 2608 to perform one or more machine learningalgorithms, neural network architectures, use cases, or trainingtechniques described herein.

FIG. 27 is a block diagram of a processor 2700 having one or moreprocessor cores 2702A-2702N, an integrated memory controller 2714, andan integrated graphics processor 2708, according to at least oneembodiment. In at least one embodiment, processor 2700 can includeadditional cores up to and including additional core 2702N representedby dashed lined boxes. In at least one embodiment, each of processorcores 2702A-2702N includes one or more internal cache units 2704A-2704N.In at least one embodiment, each processor core also has access to oneor more shared cached units 2706.

In at least one embodiment, internal cache units 2704A-2704N and sharedcache units 2706 represent a cache memory hierarchy within processor2700. In at least one embodiment, cache memory units 2704A-2704N mayinclude at least one level of instruction and data cache within eachprocessor core and one or more levels of shared mid-level cache, such asa Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache,where a highest level of cache before external memory is classified asan LLC. In at least one embodiment, cache coherency logic maintainscoherency between various cache units 2706 and 2704A-2704N.

In at least one embodiment, processor 2700 may also include a set of oneor more bus controller units 2716 and a system agent core 2710. In atleast one embodiment, bus controller units 2716 manage a set ofperipheral buses, such as one or more PCI or PCI express busses. In atleast one embodiment, system agent core 2710 provides managementfunctionality for various processor components. In at least oneembodiment, system agent core 2710 includes one or more integratedmemory controllers 2714 to manage access to various external memorydevices (not shown).

In at least one embodiment, one or more of processor cores 2702A-2702Ninclude support for simultaneous multi-threading. In at least oneembodiment, system agent core 2710 includes components for coordinatingand operating cores 2702A-2702N during multi-threaded processing. In atleast one embodiment, system agent core 2710 may additionally include apower control unit (PCU), which includes logic and components toregulate one or more power states of processor cores 2702A-2702N andgraphics processor 2708.

In at least one embodiment, processor 2700 additionally includesgraphics processor 2708 to execute graphics processing operations. In atleast one embodiment, graphics processor 2708 couples with shared cacheunits 2706, and system agent core 2710, including one or more integratedmemory controllers 2714. In at least one embodiment, system agent core2710 also includes a display controller 2711 to drive graphics processoroutput to one or more coupled displays. In at least one embodiment,display controller 2711 may also be a separate module coupled withgraphics processor 2708 via at least one interconnect, or may beintegrated within graphics processor 2708.

In at least one embodiment, a ring-based interconnect unit 2712 is usedto couple internal components of processor 2700. In at least oneembodiment, an alternative interconnect unit may be used, such as apoint-to-point interconnect, a switched interconnect, or othertechniques. In at least one embodiment, graphics processor 2708 coupleswith ring interconnect 2712 via an I/O link 2713.

In at least one embodiment, I/O link 2713 represents at least one ofmultiple varieties of I/O interconnects, including an on package I/Ointerconnect which facilitates communication between various processorcomponents and a high-performance embedded memory module 2718, such asan eDRAM module. In at least one embodiment, each of processor cores2702A-2702N and graphics processor 2708 use embedded memory module 2718as a shared Last Level Cache.

In at least one embodiment, processor cores 2702A-2702N are homogeneouscores executing a common instruction set architecture. In at least oneembodiment, processor cores 2702A-2702N are heterogeneous in terms ofinstruction set architecture (ISA), where one or more of processor cores2702A-2702N execute a common instruction set, while one or more othercores of processor cores 2702A-2702N executes a subset of a commoninstruction set or a different instruction set. In at least oneembodiment, processor cores 2702A-2702N are heterogeneous in terms ofmicroarchitecture, where one or more cores having a relatively higherpower consumption couple with one or more power cores having a lowerpower consumption. In at least one embodiment, processor 2700 can beimplemented on one or more chips or as an SoC integrated circuit.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment portions or all of inference and/or training logic 115 may beincorporated into graphics processor 2708. For example, in at least oneembodiment, training and/or inferencing techniques described herein mayuse one or more of ALUs embodied in a 3D pipeline, graphics core(s)2702, shared function logic, or other logic in FIG. 27. Moreover, in atleast one embodiment, inferencing and/or training operations describedherein may be done using logic other than logic illustrated in FIG. 1Aor 1B. In at least one embodiment, weight parameters may be stored inon-chip or off-chip memory and/or registers (shown or not shown) thatconfigure ALUs of processor 2700 to perform one or more machine learningalgorithms, neural network architectures, use cases, or trainingtechniques described herein.

FIG. 28 is a block diagram of a graphics processor 2800, which may be adiscrete graphics processing unit, or may be a graphics processorintegrated with a plurality of processing cores. In at least oneembodiment, graphics processor 2800 communicates via a memory mapped I/Ointerface to registers on graphics processor 2800 and with commandsplaced into memory. In at least one embodiment, graphics processor 2800includes a memory interface 2814 to access memory. In at least oneembodiment, memory interface 2814 is an interface to local memory, oneor more internal caches, one or more shared external caches, and/or tosystem memory.

In at least one embodiment, graphics processor 2800 also includes adisplay controller 2802 to drive display output data to a display device2820. In at least one embodiment, display controller 2802 includeshardware for one or more overlay planes for display device 2820 andcomposition of multiple layers of video or user interface elements. Inat least one embodiment, display device 2820 can be an internal orexternal display device. In at least one embodiment, display device 2820is a head mounted display device, such as a virtual reality (VR) displaydevice or an augmented reality (AR) display device. In at least oneembodiment, graphics processor 2800 includes a video codec engine 2806to encode, decode, or transcode media to, from, or between one or moremedia encoding formats, including, but not limited to Moving PictureExperts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC)formats such as H.264/MPEG-4 AVC, as well as the Society of MotionPicture & Television Engineers (SMPTE) 421M/VC-1, and Joint PhotographicExperts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG)formats.

In at least one embodiment, graphics processor 2800 includes a blockimage transfer (BLIT) engine 2804 to perform two-dimensional (2D)rasterizer operations including, for example, bit-boundary blocktransfers. However, in at least one embodiment, 2D graphics operationsare performed using one or more components of a graphics processingengine (GPE) 2810. In at least one embodiment, GPE 2810 is a computeengine for performing graphics operations, including three-dimensional(3D) graphics operations and media operations.

In at least one embodiment, GPE 2810 includes a 3D pipeline 2812 forperforming 3D operations, such as rendering three-dimensional images andscenes using processing functions that act upon 3D primitive shapes(e.g., rectangle, triangle, etc.). In at least one embodiment, 3Dpipeline 2812 includes programmable and fixed function elements thatperform various tasks and/or spawn execution threads to a 3D/Mediasub-system 2815. While 3D pipeline 2812 can be used to perform mediaoperations, in at least one embodiment, GPE 2810 also includes a mediapipeline 2816 that is used to perform media operations, such as videopost-processing and image enhancement.

In at least one embodiment, media pipeline 2816 includes fixed functionor programmable logic units to perform one or more specialized mediaoperations, such as video decode acceleration, video de-interlacing, andvideo encode acceleration in place of, or on behalf of, video codecengine 2806. In at least one embodiment, media pipeline 2816additionally includes a thread spawning unit to spawn threads forexecution on 3D/Media sub-system 2815. In at least one embodiment,spawned threads perform computations for media operations on one or moregraphics execution units included in 3D/Media sub-system 2815.

In at least one embodiment, 3D/Media subsystem 2815 includes logic forexecuting threads spawned by 3D pipeline 2812 and media pipeline 2816.In at least one embodiment, 3D pipeline 2812 and media pipeline 2816send thread execution requests to 3D/Media subsystem 2815, whichincludes thread dispatch logic for arbitrating and dispatching variousrequests to available thread execution resources. In at least oneembodiment, execution resources include an array of graphics executionunits to process 3D and media threads. In at least one embodiment,3D/Media subsystem 2815 includes one or more internal caches for threadinstructions and data. In at least one embodiment, subsystem 2815 alsoincludes shared memory, including registers and addressable memory, toshare data between threads and to store output data.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment portions or all of inference and/or training logic 115 may beincorporated into graphics processor 2800. For example, in at least oneembodiment, training and/or inferencing techniques described herein mayuse one or more of ALUs embodied in 3D pipeline 2812. Moreover, in atleast one embodiment, inferencing and/or training operations describedherein may be done using logic other than logic illustrated in FIG. 1Aor 1B. In at least one embodiment, weight parameters may be stored inon-chip or off-chip memory and/or registers (shown or not shown) thatconfigure ALUs of graphics processor 2800 to perform one or more machinelearning algorithms, neural network architectures, use cases, ortraining techniques described herein.

FIG. 29 is a block diagram of a graphics processing engine 2910 of agraphics processor in accordance with at least one embodiment. In atleast one embodiment, graphics processing engine (GPE) 2910 is a versionof GPE 2810 shown in FIG. 28. In at least one embodiment, a mediapipeline 2916 is optional and may not be explicitly included within GPE2910. In at least one embodiment, a separate media and/or imageprocessor is coupled to GPE 2910.

In at least one embodiment, GPE 2910 is coupled to or includes a commandstreamer 2903, which provides a command stream to a 3D pipeline 2912and/or media pipeline 2916. In at least one embodiment, command streamer2903 is coupled to memory, which can be system memory, or one or more ofinternal cache memory and shared cache memory. In at least oneembodiment, command streamer 2903 receives commands from memory andsends commands to 3D pipeline 2912 and/or media pipeline 2916. In atleast one embodiment, commands are instructions, primitives, ormicro-operations fetched from a ring buffer, which stores commands for3D pipeline 2912 and media pipeline 2916. In at least one embodiment, aring buffer can additionally include batch command buffers storingbatches of multiple commands. In at least one embodiment, commands for3D pipeline 2912 can also include references to data stored in memory,such as, but not limited to, vertex and geometry data for 3D pipeline2912 and/or image data and memory objects for media pipeline 2916. In atleast one embodiment, 3D pipeline 2912 and media pipeline 2916 processcommands and data by performing operations or by dispatching one or moreexecution threads to a graphics core array 2914. In at least oneembodiment, graphics core array 2914 includes one or more blocks ofgraphics cores (e.g., graphics core(s) 2915A, graphics core(s) 2915B),each block including one or more graphics cores. In at least oneembodiment, each graphics core includes a set of graphics executionresources that includes general-purpose and graphics specific executionlogic to perform graphics and compute operations, as well as fixedfunction texture processing and/or machine learning and artificialintelligence acceleration logic, including inference and/or traininglogic 115 in FIG. 1A and FIG. 1B.

In at least one embodiment, 3D pipeline 2912 includes fixed function andprogrammable logic to process one or more shader programs, such asvertex shaders, geometry shaders, pixel shaders, fragment shaders,compute shaders, or other shader programs, by processing instructionsand dispatching execution threads to graphics core array 2914. In atleast one embodiment, graphics core array 2914 provides a unified blockof execution resources for use in processing shader programs. In atleast one embodiment, a multi-purpose execution logic (e.g., executionunits) within graphics core(s) 2915A-2915B of graphic core array 2914includes support for various 3D API shader languages and can executemultiple simultaneous execution threads associated with multipleshaders.

In at least one embodiment, graphics core array 2914 also includesexecution logic to perform media functions, such as video and/or imageprocessing. In at least one embodiment, execution units additionallyinclude general-purpose logic that is programmable to perform parallelgeneral-purpose computational operations, in addition to graphicsprocessing operations.

In at least one embodiment, output data generated by threads executingon graphics core array 2914 can output data to memory in a unifiedreturn buffer (URB) 2918. In at least one embodiment, URB 2918 can storedata for multiple threads. In at least one embodiment, URB 2918 may beused to send data between different threads executing on graphics corearray 2914. In at least one embodiment, URB 2918 may additionally beused for synchronization between threads on graphics core array 2914 andfixed function logic within shared function logic 2920.

In at least one embodiment, graphics core array 2914 is scalable, suchthat graphics core array 2914 includes a variable number of graphicscores, each having a variable number of execution units based on atarget power and performance level of GPE 2910. In at least oneembodiment, execution resources are dynamically scalable, such thatexecution resources may be enabled or disabled as needed.

In at least one embodiment, graphics core array 2914 is coupled toshared function logic 2920 that includes multiple resources that areshared between graphics cores in graphics core array 2914. In at leastone embodiment, shared functions performed by shared function logic 2920are embodied in hardware logic units that provide specializedsupplemental functionality to graphics core array 2914. In at least oneembodiment, shared function logic 2920 includes but is not limited to asampler unit 2921, a math unit 2922, and inter-thread communication(ITC) logic 2929. In at least one embodiment, one or more cache(s) 2925are included in, or coupled to, shared function logic 2920.

In at least one embodiment, a shared function is used if demand for aspecialized function is insufficient for inclusion within graphics corearray 2914. In at least one embodiment, a single instantiation of aspecialized function is used in shared function logic 2920 and sharedamong other execution resources within graphics core array 2914. In atleast one embodiment, specific shared functions within shared functionlogic 2920 that are used extensively by graphics core array 2914 may beincluded within shared function logic 2920 within graphics core array2914. In at least one embodiment, shared function logic 2920 withingraphics core array 2914 can include some or all logic within sharedfunction logic 2920. In at least one embodiment, all logic elementswithin shared function logic 2920 may be duplicated within sharedfunction logic 2926 of graphics core array 2914. In at least oneembodiment, shared function logic 2920 is excluded in favor of sharedfunction logic 2926 within graphics core array 2914.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment portions or all of inference and/or training logic 115 may beincorporated into graphics processor 2910. For example, in at least oneembodiment, training and/or inferencing techniques described herein mayuse one or more of ALUs embodied in 3D pipeline 2912, graphics core(s)2915, shared function logic 2926, shared function logic 2920, or otherlogic in FIG. 29. Moreover, in at least one embodiment, inferencingand/or training operations described herein may be done using logicother than logic illustrated in FIG. 1A or 1B. In at least oneembodiment, weight parameters may be stored in on-chip or off-chipmemory and/or registers (shown or not shown) that configure ALUs ofgraphics processor 2910 to perform one or more machine learningalgorithms, neural network architectures, use cases, or trainingtechniques described herein.

FIG. 30 is a block diagram of hardware logic of a graphics processorcore 3000, according to at least one embodiment described herein. In atleast one embodiment, graphics processor core 3000 is included within agraphics core array. In at least one embodiment, graphics processor core3000, sometimes referred to as a core slice, can be one or multiplegraphics cores within a modular graphics processor. In at least oneembodiment, graphics processor core 3000 is exemplary of one graphicscore slice, and a graphics processor as described herein may includemultiple graphics core slices based on target power and performanceenvelopes. In at least one embodiment, each graphics processor core 3000can include a fixed function block 3030 coupled with multiple sub-cores3001A-3001F, also referred to as sub-slices, that include modular blocksof general-purpose and fixed function logic.

In at least one embodiment, fixed function block 3030 includes ageometry and fixed function pipeline 3036 that can be shared by allsub-cores in graphics processor core 3000, for example, in lowerperformance and/or lower power graphics processor implementations. In atleast one embodiment, geometry and fixed function pipeline 3036 includesa 3D fixed function pipeline, a video front-end unit, a thread spawnerand thread dispatcher, and a unified return buffer manager, whichmanages unified return buffers.

In at least one embodiment, fixed function block 3030 also includes agraphics SoC interface 3037, a graphics microcontroller 3038, and amedia pipeline 3039. In at least one embodiment, graphics SoC interface3037 provides an interface between graphics processor core 3000 andother processor cores within a system on a chip integrated circuit. Inat least one embodiment, graphics microcontroller 3038 is a programmablesub-processor that is configurable to manage various functions ofgraphics processor core 3000, including thread dispatch, scheduling, andpre-emption. In at least one embodiment, media pipeline 3039 includeslogic to facilitate decoding, encoding, pre-processing, and/orpost-processing of multimedia data, including image and video data. Inat least one embodiment, media pipeline 3039 implements media operationsvia requests to compute or sampling logic within sub-cores 3001A-3001F.

In at least one embodiment, SoC interface 3037 enables graphicsprocessor core 3000 to communicate with general-purpose applicationprocessor cores (e.g., CPUs) and/or other components within an SoC,including memory hierarchy elements such as a shared last level cachememory, system RAM, and/or embedded on-chip or on-package DRAM. In atleast one embodiment, SoC interface 3037 can also enable communicationwith fixed function devices within an SoC, such as camera imagingpipelines, and enables use of and/or implements global memory atomicsthat may be shared between graphics processor core 3000 and CPUs withinan SoC. In at least one embodiment, graphics SoC interface 3037 can alsoimplement power management controls for graphics processor core 3000 andenable an interface between a clock domain of graphics processor core3000 and other clock domains within an SoC. In at least one embodiment,SoC interface 3037 enables receipt of command buffers from a commandstreamer and global thread dispatcher that are configured to providecommands and instructions to each of one or more graphics cores within agraphics processor. In at least one embodiment, commands andinstructions can be dispatched to media pipeline 3039, when mediaoperations are to be performed, or a geometry and fixed functionpipeline (e.g., geometry and fixed function pipeline 3036, and/or ageometry and fixed function pipeline 3014) when graphics processingoperations are to be performed.

In at least one embodiment, graphics microcontroller 3038 can beconfigured to perform various scheduling and management tasks forgraphics processor core 3000. In at least one embodiment, graphicsmicrocontroller 3038 can perform graphics and/or compute workloadscheduling on various graphics parallel engines within execution unit(EU) arrays 3002A-3002F, 3004A-3004F within sub-cores 3001A-3001F. In atleast one embodiment, host software executing on a CPU core of an SoCincluding graphics processor core 3000 can submit workloads to one ofmultiple graphic processor paths, which invokes a scheduling operationon an appropriate graphics engine. In at least one embodiment,scheduling operations include determining which workload to run next,submitting a workload to a command streamer, pre-empting existingworkloads running on an engine, monitoring progress of a workload, andnotifying host software when a workload is complete. In at least oneembodiment, graphics microcontroller 3038 can also facilitate low-poweror idle states for graphics processor core 3000, providing graphicsprocessor core 3000 with an ability to save and restore registers withingraphics processor core 3000 across low-power state transitionsindependently from an operating system and/or graphics driver softwareon a system.

In at least one embodiment, graphics processor core 3000 may havegreater than or fewer than illustrated sub-cores 3001A-3001F, up to Nmodular sub-cores. For each set of N sub-cores, in at least oneembodiment, graphics processor core 3000 can also include sharedfunction logic 3010, shared and/or cache memory 3012, geometry/fixedfunction pipeline 3014, as well as additional fixed function logic 3016to accelerate various graphics and compute processing operations. In atleast one embodiment, shared function logic 3010 can include logic units(e.g., sampler, math, and/or inter-thread communication logic) that canbe shared by each N sub-cores within graphics processor core 3000. In atleast one embodiment, shared and/or cache memory 3012 can be alast-level cache for N sub-cores 3001A-3001F within graphics processorcore 3000 and can also serve as shared memory that is accessible bymultiple sub-cores. In at least one embodiment, geometry/fixed functionpipeline 3014 can be included instead of geometry/fixed functionpipeline 3036 within fixed function block 3030 and can include similarlogic units.

In at least one embodiment, graphics processor core 3000 includesadditional fixed function logic 3016 that can include various fixedfunction acceleration logic for use by graphics processor core 3000. Inat least one embodiment, additional fixed function logic 3016 includesan additional geometry pipeline for use in position-only shading. Inposition-only shading, at least two geometry pipelines exist, whereas ina full geometry pipeline within geometry and fixed function pipelines3014, 3036, and a cull pipeline, which is an additional geometrypipeline that may be included within additional fixed function logic3016. In at least one embodiment, a cull pipeline is a trimmed downversion of a full geometry pipeline. In at least one embodiment, a fullpipeline and a cull pipeline can execute different instances of anapplication, each instance having a separate context. In at least oneembodiment, position only shading can hide long cull runs of discardedtriangles, enabling shading to be completed earlier in some instances.For example, in at least one embodiment, cull pipeline logic withinadditional fixed function logic 3016 can execute position shaders inparallel with a main application and generally generates criticalresults faster than a full pipeline, as a cull pipeline fetches andshades position attributes of vertices, without performing rasterizationand rendering of pixels to a frame buffer. In at least one embodiment, acull pipeline can use generated critical results to compute visibilityinformation for all triangles without regard to whether those trianglesare culled. In at least one embodiment, a full pipeline (which in thisinstance may be referred to as a replay pipeline) can consume visibilityinformation to skip culled triangles to shade only visible trianglesthat are finally passed to a rasterization phase.

In at least one embodiment, additional fixed function logic 3016 canalso include machine-learning acceleration logic, such as fixed functionmatrix multiplication logic, for implementations including optimizationsfor machine learning training or inferencing.

In at least one embodiment, within each graphics sub-core 3001A-3001Fincludes a set of execution resources that may be used to performgraphics, media, and compute operations in response to requests bygraphics pipeline, media pipeline, or shader programs. In at least oneembodiment, graphics sub-cores 3001A-3001F include multiple EU arrays3002A-3002F, 3004A-3004F, thread dispatch and inter-thread communication(TD/IC) logic 3003A-3003F, a 3D (e.g., texture) sampler 3005A-3005F, amedia sampler 3006A-3006F, a shader processor 3007A-3007F, and sharedlocal memory (SLM) 3008A-3008F. In at least one embodiment, EU arrays3002A-3002F, 3004A-3004F each include multiple execution units, whichare general-purpose graphics processing units capable of performingfloating-point and integer/fixed-point logic operations in service of agraphics, media, or compute operation, including graphics, media, orcompute shader programs. In at least one embodiment, TD/IC logic3003A-3003F performs local thread dispatch and thread control operationsfor execution units within a sub-core and facilitates communicationbetween threads executing on execution units of a sub-core. In at leastone embodiment, 3D samplers 3005A-3005F can read texture or other 3Dgraphics related data into memory. In at least one embodiment, 3Dsamplers can read texture data differently based on a configured samplestate and texture format associated with a given texture. In at leastone embodiment, media samplers 3006A-3006F can perform similar readoperations based on a type and format associated with media data. In atleast one embodiment, each graphics sub-core 3001A-3001F can alternatelyinclude a unified 3D and media sampler. In at least one embodiment,threads executing on execution units within each of sub-cores3001A-3001F can make use of shared local memory 3008A-3008F within eachsub-core, to enable threads executing within a thread group to executeusing a common pool of on-chip memory.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, portions or all of inference and/or training logic 115 maybe incorporated into graphics processor core 3000. For example, in atleast one embodiment, training and/or inferencing techniques describedherein may use one or more of ALUs embodied in a 3D pipeline, graphicsmicrocontroller 3038, geometry and fixed function pipeline 3014 and3036, or other logic in FIG. 30. Moreover, in at least one embodiment,inferencing and/or training operations described herein may be doneusing logic other than logic illustrated in FIG. 1A or 1B. In at leastone embodiment, weight parameters may be stored in on-chip or off-chipmemory and/or registers (shown or not shown) that configure ALUs ofgraphics processor core 3000 to perform one or more machine learningalgorithms, neural network architectures, use cases, or trainingtechniques described herein.

FIGS. 31A-31B illustrate thread execution logic 3100 including an arrayof processing elements of a graphics processor core according to atleast one embodiment. FIG. 31A illustrates at least one embodiment, inwhich thread execution logic 3100 is used. FIG. 31B illustratesexemplary internal details of a graphics execution unit 3108, accordingto at least one embodiment.

As illustrated in FIG. 31A, in at least one embodiment, thread executionlogic 3100 includes a shader processor 3102, a thread dispatcher 3104,an instruction cache 3106, a scalable execution unit array including aplurality of execution units 3107A-3107N and 3108A-3108N, a sampler3110, a data cache 3112, and a data port 3114. In at least oneembodiment, a scalable execution unit array can dynamically scale byenabling or disabling one or more execution units (e.g., any ofexecution unit 3108A-N or 3107A-N) based on computational requirementsof a workload, for example. In at least one embodiment, scalableexecution units are interconnected via an interconnect fabric that linksto each execution unit. In at least one embodiment, thread executionlogic 3100 includes one or more connections to memory, such as systemmemory or cache memory, through one or more of instruction cache 3106,data port 3114, sampler 3110, and execution units 3107 or 3108. In atleast one embodiment, each execution unit (e.g., 3107A) is a stand-aloneprogrammable general-purpose computational unit that is capable ofexecuting multiple simultaneous hardware threads while processingmultiple data elements in parallel for each thread. In at least oneembodiment, array of execution units 3107 and/or 3108 is scalable toinclude any number individual execution units.

In at least one embodiment, execution units 3107 and/or 3108 areprimarily used to execute shader programs. In at least one embodiment,shader processor 3102 can process various shader programs and dispatchexecution threads associated with shader programs via a threaddispatcher 3104. In at least one embodiment, thread dispatcher 3104includes logic to arbitrate thread initiation requests from graphics andmedia pipelines and instantiate requested threads on one or moreexecution units in execution units 3107 and/or 3108. For example, in atleast one embodiment, a geometry pipeline can dispatch vertex,tessellation, or geometry shaders to thread execution logic forprocessing. In at least one embodiment, thread dispatcher 3104 can alsoprocess runtime thread spawning requests from executing shader programs.

In at least one embodiment, execution units 3107 and/or 3108 support aninstruction set that includes native support for many standard 3Dgraphics shader instructions, such that shader programs from graphicslibraries (e.g., Direct 3D and OpenGL) are executed with a minimaltranslation. In at least one embodiment, execution units support vertexand geometry processing (e.g., vertex programs, geometry programs,and/or vertex shaders), pixel processing (e.g., pixel shaders, fragmentshaders) and general-purpose processing (e.g., compute and mediashaders). In at least one embodiment, each of execution units 3107and/or 3108, which include one or more arithmetic logic units (ALUs), iscapable of multi-issue single instruction multiple data (SIMD) executionand multi-threaded operation enables an efficient execution environmentdespite higher latency memory accesses. In at least one embodiment, eachhardware thread within each execution unit has a dedicatedhigh-bandwidth register file and associated independent thread-state. Inat least one embodiment, execution is multi-issue per clock to pipelinescapable of integer, single and double precision floating pointoperations, SIMD branch capability, logical operations, transcendentaloperations, and other miscellaneous operations. In at least oneembodiment, while waiting for data from memory or one of sharedfunctions, dependency logic within execution units 3107 and/or 3108causes a waiting thread to sleep until requested data has been returned.In at least one embodiment, while an awaiting thread is sleeping,hardware resources may be devoted to processing other threads. Forexample, in at least one embodiment, during a delay associated with avertex shader operation, an execution unit can perform operations for apixel shader, fragment shader, or another type of shader program,including a different vertex shader.

In at least one embodiment, each execution unit in execution units 3107and/or 3108 operates on arrays of data elements. In at least oneembodiment, a number of data elements is an “execution size,” or numberof channels for an instruction. In at least one embodiment, an executionchannel is a logical unit of execution for data element access, masking,and flow control within instructions. In at least one embodiment, anumber of channels may be independent of a number of physical arithmeticlogic units (ALUs) or floating point units (FPUs) for a particulargraphics processor. In at least one embodiment, execution units 3107and/or 3108 support integer and floating-point data types.

In at least one embodiment, an execution unit instruction set includesSIMD instructions. In at least one embodiment, various data elements canbe stored as a packed data type in a register and execution unit willprocess various elements based on data size of elements. For example, inat least one embodiment, when operating on a 256-bit wide vector, 256bits of a vector are stored in a register and an execution unit operateson a vector as four separate 64-bit packed data elements (Quad-Word (QW)size data elements), eight separate 32-bit packed data elements (DoubleWord (DW) size data elements), sixteen separate 16-bit packed dataelements (Word (W) size data elements), or thirty-two separate 8-bitdata elements (byte (B) size data elements). However, in at least oneembodiment, different vector widths and register sizes are possible.

In at least one embodiment, one or more execution units can be combinedinto a fused execution unit 3109A-3109N having thread control logic(3111A-3111N) that is common to fused EUs such as execution unit 3107Afused with execution unit 3108A into fused execution unit 3109A. In atleast one embodiment, multiple EUs can be fused into an EU group. In atleast one embodiment, each EU in a fused EU group can be configured toexecute a separate SIMD hardware thread, with a number of EUs in a fusedEU group possibly varying according to various embodiments. In at leastone embodiment, various SIMD widths can be performed per-EU, includingbut not limited to SIMD8, SIMD16, and SIMD32. In at least oneembodiment, each fused graphics execution unit 3109A-3109N includes atleast two execution units. For example, in at least one embodiment,fused execution unit 3109A includes a first EU 3107A, second EU 3108A,and thread control logic 3111A that is common to first EU 3107A andsecond EU 3108A. In at least one embodiment, thread control logic 3111Acontrols threads executed on fused graphics execution unit 3109A,allowing each EU within fused execution units 3109A-3109N to executeusing a common instruction pointer register.

In at least one embodiment, one or more internal instruction caches(e.g., 3106) are included in thread execution logic 3100 to cache threadinstructions for execution units. In at least one embodiment, one ormore data caches (e.g., 3112) are included to cache thread data duringthread execution. In at least one embodiment, sampler 3110 is includedto provide texture sampling for 3D operations and media sampling formedia operations. In at least one embodiment, sampler 3110 includesspecialized texture or media sampling functionality to process textureor media data during sampling process before providing sampled data toan execution unit.

During execution, in at least one embodiment, graphics and mediapipelines send thread initiation requests to thread execution logic 3100via thread spawning and dispatch logic. In at least one embodiment, oncea group of geometric objects has been processed and rasterized intopixel data, pixel processor logic (e.g., pixel shader logic, fragmentshader logic, etc.) within shader processor 3102 is invoked to furthercompute output information and cause results to be written to outputsurfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). Inat least one embodiment, a pixel shader or a fragment shader calculatesvalues of various vertex attributes that are to be interpolated across arasterized object. In at least one embodiment, pixel processor logicwithin shader processor 3102 then executes an application programminginterface (API)-supplied pixel or fragment shader program. In at leastone embodiment, to execute a shader program, shader processor 3102dispatches threads to an execution unit (e.g., 3108A) via threaddispatcher 3104. In at least one embodiment, shader processor 3102 usestexture sampling logic in sampler 3110 to access texture data in texturemaps stored in memory. In at least one embodiment, arithmetic operationson texture data and input geometry data compute pixel color data foreach geometric fragment, or discards one or more pixels from furtherprocessing.

In at least one embodiment, data port 3114 provides a memory accessmechanism for thread execution logic 3100 to output processed data tomemory for further processing on a graphics processor output pipeline.In at least one embodiment, data port 3114 includes or couples to one ormore cache memories (e.g., data cache 3112) to cache data for memoryaccess via a data port.

As illustrated in FIG. 31B, in at least one embodiment, a graphicsexecution unit 3108 can include an instruction fetch unit 3137, ageneral register file array (GRF) 3124, an architectural register filearray (ARF) 3126, a thread arbiter 3122, a send unit 3130, a branch unit3132, a set of SIMD floating point units (FPUs) 3134, and a set ofdedicated integer SIMD ALUs 3135. In at least one embodiment, GRF 3124and ARF 3126 includes a set of general register files and architectureregister files associated with each simultaneous hardware thread thatmay be active in graphics execution unit 3108. In at least oneembodiment, per thread architectural state is maintained in ARF 3126,while data used during thread execution is stored in GRF 3124. In atleast one embodiment, execution state of each thread, includinginstruction pointers for each thread, can be held in thread-specificregisters in ARF 3126.

In at least one embodiment, graphics execution unit 3108 has anarchitecture that is a combination of Simultaneous Multi-Threading (SMT)and fine-grained Interleaved Multi-Threading (IMT). In at least oneembodiment, architecture has a modular configuration that can befine-tuned at design time based on a target number of simultaneousthreads and number of registers per execution unit, where execution unitresources are divided across logic used to execute multiple simultaneousthreads.

In at least one embodiment, graphics execution unit 3108 can co-issuemultiple instructions, which may each be different instructions. In atleast one embodiment, thread arbiter 3122 of graphics execution unitthread 3108 can dispatch instructions to one of send unit 3130, branchunit 3132, or SIMD FPU(s) 3134 for execution. In at least oneembodiment, each execution thread can access 128 general-purposeregisters within GRF 3124, where each register can store 32 bytes,accessible as a SIMD 8-element vector of 32-bit data elements. In atleast one embodiment, each execution unit thread has access to 4kilobytes within GRF 3124, although embodiments are not so limited, andgreater or fewer register resources may be provided in otherembodiments. In at least one embodiment, up to seven threads can executesimultaneously, although a number of threads per execution unit can alsovary according to embodiments. In at least one embodiment, in whichseven threads may access 4 kilobytes, GRF 3124 can store a total of 28kilobytes. In at least one embodiment, flexible addressing modes canpermit registers to be addressed together to build effectively widerregisters or to represent strided rectangular block data structures.

In at least one embodiment, memory operations, sampler operations, andother longer-latency system communications are dispatched via “send”instructions that are executed by message passing to send unit 3130. Inat least one embodiment, branch instructions are dispatched to branchunit 3132 to facilitate SIMD divergence and eventual convergence.

In at least one embodiment, graphics execution unit 3108 includes one ormore SIMD floating point units (FPU(s)) 3134 to perform floating-pointoperations. In at least one embodiment, FPU(s) 3134 also support integercomputation. In at least one embodiment, FPU(s) 3134 can SIMD execute upto M number of 32-bit floating-point (or integer) operations, or SIMDexecute up to 2M 16-bit integer or 16-bit floating-point operations. Inat least one embodiment, at least one FPU provides extended mathcapability to support high-throughput transcendental math functions anddouble precision 64-bit floating-point. In at least one embodiment, aset of 8-bit integer SIMD ALUs 3135 are also present, and may bespecifically optimized to perform operations associated with machinelearning computations.

In at least one embodiment, arrays of multiple instances of graphicsexecution unit 3108 can be instantiated in a graphics sub-core grouping(e.g., a sub-slice). In at least one embodiment, execution unit 3108 canexecute instructions across a plurality of execution channels. In atleast one embodiment, each thread executed on graphics execution unit3108 is executed on a different channel.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, portions or all of inference and/or training logic 115 maybe incorporated into thread execution logic 3100. Moreover, in at leastone embodiment, inferencing and/or training operations described hereinmay be done using logic other than logic illustrated in FIG. 1A or 1B.In at least one embodiment, weight parameters may be stored in on-chipor off-chip memory and/or registers (shown or not shown) that configureALUs thread of execution logic 3100 to perform one or more machinelearning algorithms, neural network architectures, use cases, ortraining techniques described herein.

FIG. 32 illustrates a parallel processing unit (“PPU”) 3200, accordingto at least one embodiment. In at least one embodiment, PPU 3200 isconfigured with machine-readable code that, if executed by PPU 3200,causes PPU 3200 to perform some or all of processes and techniquesdescribed throughout this disclosure. In at least one embodiment, PPU3200 is a multi-threaded processor that is implemented on one or moreintegrated circuit devices and that utilizes multithreading as alatency-hiding technique designed to process computer-readableinstructions (also referred to as machine-readable instructions orsimply instructions) on multiple threads in parallel. In at least oneembodiment, a thread refers to a thread of execution and is aninstantiation of a set of instructions configured to be executed by PPU3200. In at least one embodiment, PPU 3200 is a graphics processing unit(“GPU”) configured to implement a graphics rendering pipeline forprocessing three-dimensional (“3D”) graphics data in order to generatetwo-dimensional (“2D”) image data for display on a display device suchas a liquid crystal display (“LCD”) device. In at least one embodiment,PPU 3200 is utilized to perform computations such as linear algebraoperations and machine-learning operations. FIG. 32 illustrates anexample parallel processor for illustrative purposes only and should beconstrued as a non-limiting example of processor architecturescontemplated within scope of this disclosure and that any suitableprocessor may be employed to supplement and/or substitute for same.

In at least one embodiment, one or more PPUs 3200 are configured toaccelerate High Performance Computing (“HPC”), data center, and machinelearning applications. In at least one embodiment, PPU 3200 isconfigured to accelerate deep learning systems and applicationsincluding following non-limiting examples: autonomous vehicle platforms,deep learning, high-accuracy speech, image, text recognition systems,intelligent video analytics, molecular simulations, drug discovery,disease diagnosis, weather forecasting, big data analytics, astronomy,molecular dynamics simulation, financial modeling, robotics, factoryautomation, real-time language translation, online search optimizations,and personalized user recommendations, and more.

In at least one embodiment, PPU 3200 includes, without limitation, anInput/Output (“I/O”) unit 3206, a front-end unit 3210, a scheduler unit3212, a work distribution unit 3214, a hub 3216, a crossbar (“XBar”)3220, one or more general processing clusters (“GPCs”) 3218, and one ormore partition units (“memory partition units”) 3222. In at least oneembodiment, PPU 3200 is connected to a host processor or other PPUs 3200via one or more high-speed GPU interconnects (“GPU interconnects”) 3208.In at least one embodiment, PPU 3200 is connected to a host processor orother peripheral devices via a system bus 3202. In at least oneembodiment, PPU 3200 is connected to a local memory comprising one ormore memory devices (“memory”) 3204. In at least one embodiment, memorydevices 3204 include, without limitation, one or more dynamic randomaccess memory (“DRAM”) devices. In at least one embodiment, one or moreDRAM devices are configured and/or configurable as high-bandwidth memory(“HBM”) subsystems, with multiple DRAM dies stacked within each device.

In at least one embodiment, high-speed GPU interconnect 3208 may referto a wire-based multi-lane communications link that is used by systemsto scale and include one or more PPUs 3200 combined with one or morecentral processing units (“CPUs”), supports cache coherence between PPUs3200 and CPUs, and CPU mastering. In at least one embodiment, dataand/or commands are transmitted by high-speed GPU interconnect 3208through hub 3216 to/from other units of PPU 3200 such as one or morecopy engines, video encoders, video decoders, power management units,and other components which may not be explicitly illustrated in FIG. 32.

In at least one embodiment, I/O unit 3206 is configured to transmit andreceive communications (e.g., commands, data) from a host processor (notillustrated in FIG. 32) over system bus 3202. In at least oneembodiment, I/O unit 3206 communicates with host processor directly viasystem bus 3202 or through one or more intermediate devices such as amemory bridge. In at least one embodiment, I/O unit 3206 may communicatewith one or more other processors, such as one or more of PPUs 3200 viasystem bus 3202. In at least one embodiment, I/O unit 3206 implements aPeripheral Component Interconnect Express (“PCIe”) interface forcommunications over a PCIe bus. In at least one embodiment, I/O unit3206 implements interfaces for communicating with external devices.

In at least one embodiment, I/O unit 3206 decodes packets received viasystem bus 3202. In at least one embodiment, at least some packetsrepresent commands configured to cause PPU 3200 to perform variousoperations. In at least one embodiment, I/O unit 3206 transmits decodedcommands to various other units of PPU 3200 as specified by commands. Inat least one embodiment, commands are transmitted to front-end unit 3210and/or transmitted to hub 3216 or other units of PPU 3200 such as one ormore copy engines, a video encoder, a video decoder, a power managementunit, etc. (not explicitly illustrated in FIG. 32). In at least oneembodiment, I/O unit 3206 is configured to route communications betweenand among various logical units of PPU 3200.

In at least one embodiment, a program executed by host processor encodesa command stream in a buffer that provides workloads to PPU 3200 forprocessing. In at least one embodiment, a workload comprisesinstructions and data to be processed by those instructions. In at leastone embodiment, a buffer is a region in a memory that is accessible(e.g., read/write) by both a host processor and PPU 3200—a hostinterface unit may be configured to access that buffer in a systemmemory connected to system bus 3202 via memory requests transmitted oversystem bus 3202 by I/O unit 3206. In at least one embodiment, a hostprocessor writes a command stream to a buffer and then transmits apointer to a start of a command stream to PPU 3200 such that front-endunit 3210 receives pointers to one or more command streams and managesone or more command streams, reading commands from command streams andforwarding commands to various units of PPU 3200.

In at least one embodiment, front-end unit 3210 is coupled to schedulerunit 3212 that configures various GPCs 3218 to process tasks defined byone or more command streams. In at least one embodiment, scheduler unit3212 is configured to track state information related to various tasksmanaged by scheduler unit 3212 where state information may indicatewhich of GPCs 3218 a task is assigned to, whether task is active orinactive, a priority level associated with task, and so forth. In atleast one embodiment, scheduler unit 3212 manages execution of aplurality of tasks on one or more of GPCs 3218.

In at least one embodiment, scheduler unit 3212 is coupled to workdistribution unit 3214 that is configured to dispatch tasks forexecution on GPCs 3218. In at least one embodiment, work distributionunit 3214 tracks a number of scheduled tasks received from schedulerunit 3212 and work distribution unit 3214 manages a pending task pooland an active task pool for each of GPCs 3218. In at least oneembodiment, pending task pool comprises a number of slots (e.g., 32slots) that contain tasks assigned to be processed by a particular GPC3218; an active task pool may comprise a number of slots (e.g., 4 slots)for tasks that are actively being processed by GPCs 3218 such that asone of GPCs 3218 completes execution of a task, that task is evictedfrom that active task pool for GPC 3218 and another task from a pendingtask pool is selected and scheduled for execution on GPC 3218. In atleast one embodiment, if an active task is idle on GPC 3218, such aswhile waiting for a data dependency to be resolved, then that activetask is evicted from GPC 3218 and returned to that pending task poolwhile another task in that pending task pool is selected and scheduledfor execution on GPC 3218.

In at least one embodiment, work distribution unit 3214 communicateswith one or more GPCs 3218 via XBar 3220. In at least one embodiment,XBar 3220 is an interconnect network that couples many of units of PPU3200 to other units of PPU 3200 and can be configured to couple workdistribution unit 3214 to a particular GPC 3218. In at least oneembodiment, one or more other units of PPU 3200 may also be connected toXBar 3220 via hub 3216.

In at least one embodiment, tasks are managed by scheduler unit 3212 anddispatched to one of GPCs 3218 by work distribution unit 3214. In atleast one embodiment, GPC 3218 is configured to process task andgenerate results. In at least one embodiment, results may be consumed byother tasks within GPC 3218, routed to a different GPC 3218 via XBar3220, or stored in memory 3204. In at least one embodiment, results canbe written to memory 3204 via partition units 3222, which implement amemory interface for reading and writing data to/from memory 3204. In atleast one embodiment, results can be transmitted to another PPU 3200 orCPU via high-speed GPU interconnect 3208. In at least one embodiment,PPU 3200 includes, without limitation, a number U of partition units3222 that is equal to a number of separate and distinct memory devices3204 coupled to PPU 3200, as described in more detail herein inconjunction with FIG. 34.

In at least one embodiment, a host processor executes a driver kernelthat implements an application programming interface (“API”) thatenables one or more applications executing on a host processor toschedule operations for execution on PPU 3200. In at least oneembodiment, multiple compute applications are simultaneously executed byPPU 3200 and PPU 3200 provides isolation, quality of service (“QoS”),and independent address spaces for multiple compute applications. In atleast one embodiment, an application generates instructions (e.g., inform of API calls) that cause a driver kernel to generate one or moretasks for execution by PPU 3200 and that driver kernel outputs tasks toone or more streams being processed by PPU 3200. In at least oneembodiment, each task comprises one or more groups of related threads,which may be referred to as a warp. In at least one embodiment, a warpcomprises a plurality of related threads (e.g., 32 threads) that can beexecuted in parallel. In at least one embodiment, cooperating threadscan refer to a plurality of threads including instructions to performtask and that exchange data through shared memory. In at least oneembodiment, threads and cooperating threads are described in more detailin conjunction with FIG. 34.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, deep learning application processor is used to train amachine learning model, such as a neural network, to predict or inferinformation provided to PPU 3200. In at least one embodiment, PPU 3200is used to infer or predict information based on a trained machinelearning model (e.g., neural network) that has been trained by anotherprocessor or system or by PPU 3200. In at least one embodiment, PPU 3200may be used to perform one or more neural network use cases describedherein.

FIG. 33 illustrates a general processing cluster (“GPC”) 3300, accordingto at least one embodiment. In at least one embodiment, GPC 3300 is GPC3218 of FIG. 32. In at least one embodiment, each GPC 3300 includes,without limitation, a number of hardware units for processing tasks andeach GPC 3300 includes, without limitation, a pipeline manager 3302, apre-raster operations unit (“preROP”) 3304, a raster engine 3308, a workdistribution crossbar (“WDX”) 3316, a memory management unit (“MMU”)3318, one or more Data Processing Clusters (“DPCs”) 3306, and anysuitable combination of parts.

In at least one embodiment, operation of GPC 3300 is controlled bypipeline manager 3302. In at least one embodiment, pipeline manager 3302manages configuration of one or more DPCs 3306 for processing tasksallocated to GPC 3300. In at least one embodiment, pipeline manager 3302configures at least one of one or more DPCs 3306 to implement at least aportion of a graphics rendering pipeline. In at least one embodiment,DPC 3306 is configured to execute a vertex shader program on aprogrammable streaming multi-processor (“SM”) 3314. In at least oneembodiment, pipeline manager 3302 is configured to route packetsreceived from a work distribution unit to appropriate logical unitswithin GPC 3300, in at least one embodiment, and some packets may berouted to fixed function hardware units in preROP 3304 and/or rasterengine 3308 while other packets may be routed to DPCs 3306 forprocessing by a primitive engine 3312 or SM 3314. In at least oneembodiment, pipeline manager 3302 configures at least one of DPCs 3306to implement a neural network model and/or a computing pipeline.

In at least one embodiment, preROP unit 3304 is configured, in at leastone embodiment, to route data generated by raster engine 3308 and DPCs3306 to a Raster Operations (“ROP”) unit in partition unit 3222,described in more detail above in conjunction with FIG. 32. In at leastone embodiment, preROP unit 3304 is configured to perform optimizationsfor color blending, organize pixel data, perform address translations,and more. In at least one embodiment, raster engine 3308 includes,without limitation, a number of fixed function hardware units configuredto perform various raster operations, in at least one embodiment, andraster engine 3308 includes, without limitation, a setup engine, acoarse raster engine, a culling engine, a clipping engine, a fine rasterengine, a tile coalescing engine, and any suitable combination thereof.In at least one embodiment, setup engine receives transformed verticesand generates plane equations associated with geometric primitivedefined by vertices; plane equations are transmitted to a coarse rasterengine to generate coverage information (e.g., an x, y coverage mask fora tile) for primitive; output of a coarse raster engine is transmittedto a culling engine where fragments associated with a primitive thatfail a z-test are culled, and transmitted to a clipping engine wherefragments lying outside a viewing frustum are clipped. In at least oneembodiment, fragments that survive clipping and culling are passed to afine raster engine to generate attributes for pixel fragments based onplane equations generated by a setup engine. In at least one embodiment,an output of raster engine 3308 comprises fragments to be processed byany suitable entity, such as by a fragment shader implemented within DPC3306.

In at least one embodiment, each DPC 3306 included in GPC 3300comprises, without limitation, an M-Pipe Controller (“MPC”) 3310;primitive engine 3312; one or more SMs 3314; and any suitablecombination thereof. In at least one embodiment, MPC 3310 controlsoperation of DPC 3306, routing packets received from pipeline manager3302 to appropriate units in DPC 3306. In at least one embodiment,packets associated with a vertex are routed to primitive engine 3312,which is configured to fetch vertex attributes associated with a vertexfrom memory; in contrast, packets associated with a shader program maybe transmitted to SM 3314.

In at least one embodiment, SM 3314 comprises, without limitation, aprogrammable streaming processor that is configured to process tasksrepresented by a number of threads. In at least one embodiment, SM 3314is multi-threaded and configured to execute a plurality of threads(e.g., 32 threads) from a particular group of threads concurrently andimplements a Single-Instruction, Multiple-Data (“SIMD”) architecturewhere each thread in a group of threads (e.g., a warp) is configured toprocess a different set of data based on same set of instructions. In atleast one embodiment, all threads in group of threads execute a commonset of instructions. In at least one embodiment, SM 3314 implements aSingle-Instruction, Multiple Thread (“SIMT”) architecture wherein eachthread in a group of threads is configured to process a different set ofdata based on that common set of instructions, but where individualthreads in a group of threads are allowed to diverge during execution.In at least one embodiment, a program counter, call stack, and executionstate is maintained for each warp, enabling concurrency between warpsand serial execution within warps when threads within a warp diverge. Inat least one embodiment, a program counter, call stack, and executionstate is maintained for each individual thread, enabling equalconcurrency between all threads, within and between warps. In at leastone embodiment, execution state is maintained for each individual threadand threads executing common instructions may be converged and executedin parallel for better efficiency. At least one embodiment of SM 3314 isdescribed in more detail herein.

In at least one embodiment, MMU 3318 provides an interface between GPC3300 and a memory partition unit (e.g., partition unit 3222 of FIG. 32)and MMU 3318 provides translation of virtual addresses into physicaladdresses, memory protection, and arbitration of memory requests. In atleast one embodiment, MMU 3318 provides one or more translationlookaside buffers (“TLBs”) for performing translation of virtualaddresses into physical addresses in memory.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, deep learning application processor is used to train amachine learning model, such as a neural network, to predict or inferinformation provided to GPC 3300. In at least one embodiment, GPC 3300is used to infer or predict information based on a trained machinelearning model (e.g., neural network) that has been trained by anotherprocessor or system or by GPC 3300. In at least one embodiment, GPC 3300may be used to perform one or more neural network use cases describedherein.

FIG. 34 illustrates a memory partition unit 3400 of a parallelprocessing unit (“PPU”), in accordance with at least one embodiment. Inat least one embodiment, memory partition unit 3400 includes, withoutlimitation, a Raster Operations (“ROP”) unit 3402, a level two (“L2”)cache 3404, a memory interface 3406, and any suitable combinationthereof. In at least one embodiment, memory interface 3406 is coupled tomemory. In at least one embodiment, memory interface 3406 may implement32, 64, 134, 1024-bit data buses, or like, for high-speed data transfer.In at least one embodiment, PPU incorporates U memory interfaces 3406where U is a positive integer, with one memory interface 3406 per pairof partition units 3400, where each pair of partition units 3400 isconnected to a corresponding memory device. For example, in at least oneembodiment, PPU may be connected to up to Y memory devices, such as highbandwidth memory stacks or graphics double-data-rate, version 5,synchronous dynamic random access memory (“GDDR5 SDRAM”).

In at least one embodiment, memory interface 3406 implements a highbandwidth memory second generation (“HBM2”) memory interface and Yequals half of U. In at least one embodiment, HBM2 memory stacks arelocated on a physical package with a PPU, providing substantial powerand area savings compared with conventional GDDR5 SDRAM systems. In atleast one embodiment, each HBM2 stack includes, without limitation, fourmemory dies with Y=4, with each HBM2 stack including two 128-bitchannels per die for a total of 8 channels and a data bus width of 1024bits. In at least one embodiment, that memory supports Single-ErrorCorrecting Double-Error Detecting (“SECDED”) Error Correction Code(“ECC”) to protect data. In at least one embodiment, ECC can providehigher reliability for compute applications that are sensitive to datacorruption.

In at least one embodiment, PPU implements a multi-level memoryhierarchy. In at least one embodiment, memory partition unit 3400supports a unified memory to provide a single unified virtual addressspace for central processing unit (“CPU”) and PPU memory, enabling datasharing between virtual memory systems. In at least one embodimentfrequency of accesses by a PPU to a memory located on other processorsis traced to ensure that memory pages are moved to physical memory ofPPU that is accessing pages more frequently. In at least one embodiment,high-speed GPU interconnect 3208 supports address translation servicesallowing PPU to directly access a CPU's page tables and providing fullaccess to CPU memory by a PPU.

In at least one embodiment, copy engines transfer data between multiplePPUs or between PPUs and CPUs. In at least one embodiment, copy enginescan generate page faults for addresses that are not mapped into pagetables and memory partition unit 3400 then services page faults, mappingaddresses into page table, after which copy engine performs a transfer.In at least one embodiment, memory is pinned (i.e., non-pageable) formultiple copy engine operations between multiple processors,substantially reducing available memory. In at least one embodiment,with hardware page faulting, addresses can be passed to copy engineswithout regard as to whether memory pages are resident, and a copyprocess is transparent.

Data from memory 3204 of FIG. 32 or other system memory is fetched bymemory partition unit 3400 and stored in L2 cache 3404, which is locatedon-chip and is shared between various GPCs, in accordance with at leastone embodiment. Each memory partition unit 3400, in at least oneembodiment, includes, without limitation, at least a portion of L2 cacheassociated with a corresponding memory device. In at least oneembodiment, lower level caches are implemented in various units withinGPCs. In at least one embodiment, each of SMs 2714 in FIG. 33 mayimplement a Level 1 (“L1”) cache wherein that L1 cache is private memorythat is dedicated to a particular SM 2714 and data from L2 cache 3404 isfetched and stored in each L1 cache for processing in functional unitsof SMs 2714. In at least one embodiment, L2 cache 3404 is coupled tomemory interface 3406 and XBar 3220 shown in FIG. 32.

ROP unit 3402 performs graphics raster operations related to pixelcolor, such as color compression, pixel blending, and more, in at leastone embodiment. ROP unit 3402, in at least one embodiment, implementsdepth testing in conjunction with raster engine 3308, receiving a depthfor a sample location associated with a pixel fragment from a cullingengine of raster engine 3308. In at least one embodiment, depth istested against a corresponding depth in a depth buffer for a samplelocation associated with a fragment. In at least one embodiment, if thatfragment passes that depth test for that sample location, then ROP unit3402 updates depth buffer and transmits a result of that depth test toraster engine 3308. It will be appreciated that a number of partitionunits 3400 may be different than a number of GPCs and, therefore, eachROP unit 3402 can, in at least one embodiment, be coupled to each GPC.In at least one embodiment, ROP unit 3402 tracks packets received fromdifferent GPCs and determines whether a result generated by ROP unit3402 is to be routed to through XBar 3220.

FIG. 35 illustrates a streaming multi-processor (“SM”) 3500, accordingto at least one embodiment. In at least one embodiment, SM 3500 is SM ofFIG. 33. In at least one embodiment, SM 3500 includes, withoutlimitation, an instruction cache 3502, one or more scheduler units 3504,a register file 3508, one or more processing cores (“cores”) 3510, oneor more special function units (“SFUs”) 3512, one or more load/storeunits (“LSUs”) 3514, an interconnect network 3516, a shared memory/levelone (“L1”) cache 3518, and/or any suitable combination thereof.

In at least one embodiment, a work distribution unit dispatches tasksfor execution on general processing clusters (“GPCs”) of parallelprocessing units (“PPUs”) and each task is allocated to a particularData Processing Cluster (“DPC”) within a GPC and, if a task isassociated with a shader program, that task is allocated to one of SMs3500. In at least one embodiment, scheduler unit 3504 receives tasksfrom a work distribution unit and manages instruction scheduling for oneor more thread blocks assigned to SM 3500. In at least one embodiment,scheduler unit 3504 schedules thread blocks for execution as warps ofparallel threads, wherein each thread block is allocated at least onewarp. In at least one embodiment, each warp executes threads. In atleast one embodiment, scheduler unit 3504 manages a plurality ofdifferent thread blocks, allocating warps to different thread blocks andthen dispatching instructions from plurality of different cooperativegroups to various functional units (e.g., processing cores 3510, SFUs3512, and LSUs 3514) during each clock cycle.

In at least one embodiment, Cooperative Groups may refer to aprogramming model for organizing groups of communicating threads thatallows developers to express granularity at which threads arecommunicating, enabling expression of richer, more efficient paralleldecompositions. In at least one embodiment, cooperative launch APIssupport synchronization amongst thread blocks for execution of parallelalgorithms. In at least one embodiment, applications of conventionalprogramming models provide a single, simple construct for synchronizingcooperating threads: a barrier across all threads of a thread block(e.g., syncthreads( ) function). However, in at least one embodiment,programmers may define groups of threads at smaller than thread blockgranularities and synchronize within defined groups to enable greaterperformance, design flexibility, and software reuse in form ofcollective group-wide function interfaces. In at least one embodiment,Cooperative Groups enables programmers to define groups of threadsexplicitly at sub-block (i.e., as small as a single thread) andmulti-block granularities, and to perform collective operations such assynchronization on threads in a cooperative group. In at least oneembodiment, that programming model supports clean composition acrosssoftware boundaries, so that libraries and utility functions cansynchronize safely within their local context without having to makeassumptions about convergence. In at least one embodiment, CooperativeGroups primitives enable new patterns of cooperative parallelism,including, without limitation, producer-consumer parallelism,opportunistic parallelism, and global synchronization across an entiregrid of thread blocks.

In at least one embodiment, a dispatch unit 3506 is configured totransmit instructions to one or more functional units and scheduler unit3504 and includes, without limitation, two dispatch units 3506 thatenable two different instructions from a common warp to be dispatchedduring each clock cycle. In at least one embodiment, each scheduler unit3504 includes a single dispatch unit 3506 or additional dispatch units3506.

In at least one embodiment, each SM 3500, in at least one embodiment,includes, without limitation, register file 3508 that provides a set ofregisters for functional units of SM 3500. In at least one embodiment,register file 3508 is divided between each functional unit such thateach functional unit is allocated a dedicated portion of register file3508. In at least one embodiment, register file 3508 is divided betweendifferent warps being executed by SM 3500 and register file 3508provides temporary storage for operands connected to data paths offunctional units. In at least one embodiment, each SM 3500 comprises,without limitation, a plurality of L processing cores 3510, where L is apositive integer. In at least one embodiment, SM 3500 includes, withoutlimitation, a large number (e.g., 128 or more) of distinct processingcores 3510. In at least one embodiment, each processing core 3510includes, without limitation, a fully-pipelined, single-precision,double-precision, and/or mixed precision processing unit that includes,without limitation, a floating point arithmetic logic unit and aninteger arithmetic logic unit. In at least one embodiment, floatingpoint arithmetic logic units implement IEEE 754-2008 standard forfloating point arithmetic. In at least one embodiment, processing cores3510 include, without limitation, 64 single-precision (32-bit) floatingpoint cores, 64 integer cores, 32 double-precision (64-bit) floatingpoint cores, and 8 tensor cores.

Tensor cores are configured to perform matrix operations in accordancewith at least one embodiment. In at least one embodiment, one or moretensor cores are included in processing cores 3510. In at least oneembodiment, tensor cores are configured to perform deep learning matrixarithmetic, such as convolution operations for neural network trainingand inferencing. In at least one embodiment, each tensor core operateson a 4×4 matrix and performs a matrix multiply and accumulate operation,D=A×B+C, where A, B, C, and D are 4×4 matrices.

In at least one embodiment, matrix multiply inputs A and B are 16-bitfloating point matrices and accumulation matrices C and D are 16-bitfloating point or 32-bit floating point matrices. In at least oneembodiment, tensor cores operate on 16-bit floating point input datawith 32-bit floating point accumulation. In at least one embodiment,16-bit floating point multiply uses 64 operations and results in a fullprecision product that is then accumulated using 32-bit floating pointaddition with other intermediate products for a 4×4×4 matrix multiply.Tensor cores are used to perform much larger two-dimensional or higherdimensional matrix operations, built up from these smaller elements, inat least one embodiment. In at least one embodiment, an API, such as aCUDA 9 C++ API, exposes specialized matrix load, matrix multiply andaccumulate, and matrix store operations to efficiently use tensor coresfrom a CUDA-C++ program. In at least one embodiment, at a CUDA level, awarp-level interface assumes 16×16 size matrices spanning all 32 threadsof warp.

In at least one embodiment, each SM 3500 comprises, without limitation,M SFUs 3512 that perform special functions (e.g., attribute evaluation,reciprocal square root, and like). In at least one embodiment, SFUs 3512include, without limitation, a tree traversal unit configured totraverse a hierarchical tree data structure. In at least one embodiment,SFUs 3512 include, without limitation, a texture unit configured toperform texture map filtering operations. In at least one embodiment,texture units are configured to load texture maps (e.g., a 2D array oftexels) from memory and sample texture maps to produce sampled texturevalues for use in shader programs executed by SM 3500. In at least oneembodiment, texture maps are stored in shared memory/L1 cache 3518. Inat least one embodiment, texture units implement texture operations suchas filtering operations using mip-maps (e.g., texture maps of varyinglevels of detail), in accordance with at least one embodiment. In atleast one embodiment, each SM 3500 includes, without limitation, twotexture units.

Each SM 3500 comprises, without limitation, N LSUs 3514 that implementload and store operations between shared memory/L1 cache 3518 andregister file 3508, in at least one embodiment. Interconnect network3516 connects each functional unit to register file 3508 and LSU 3514 toregister file 3508 and shared memory/L1 cache 3518 in at least oneembodiment. In at least one embodiment, interconnect network 3516 is acrossbar that can be configured to connect any functional units to anyregisters in register file 3508 and connect LSUs 3514 to register file3508 and memory locations in shared memory/L1 cache 3518.

In at least one embodiment, shared memory/L1 cache 3518 is an array ofon-chip memory that allows for data storage and communication between SM3500 and primitive engine and between threads in SM 3500, in at leastone embodiment. In at least one embodiment, shared memory/L1 cache 3518comprises, without limitation, 128 KB of storage capacity and is in apath from SM 3500 to a partition unit. In at least one embodiment,shared memory/L1 cache 3518, in at least one embodiment, is used tocache reads and writes. In at least one embodiment, one or more ofshared memory/L1 cache 3518, L2 cache, and memory are backing stores.

Combining data cache and shared memory functionality into a singlememory block provides improved performance for both types of memoryaccesses, in at least one embodiment. In at least one embodiment,capacity is used or is usable as a cache by programs that do not useshared memory, such as if shared memory is configured to use half of acapacity, and texture and load/store operations can use remainingcapacity. Integration within shared memory/L1 cache 3518 enables sharedmemory/L1 cache 3518 to function as a high-throughput conduit forstreaming data while simultaneously providing high-bandwidth andlow-latency access to frequently reused data, in accordance with atleast one embodiment. In at least one embodiment, when configured forgeneral purpose parallel computation, a simpler configuration can beused compared with graphics processing. In at least one embodiment,fixed function graphics processing units are bypassed, creating a muchsimpler programming model. In a general purpose parallel computationconfiguration, a work distribution unit assigns and distributes blocksof threads directly to DPCs, in at least one embodiment. In at least oneembodiment, threads in a block execute a common program, using a uniquethread ID in calculation to ensure each thread generates unique results,using SM 3500 to execute program and perform calculations, sharedmemory/L1 cache 3518 to communicate between threads, and LSU 3514 toread and write global memory through shared memory/L1 cache 3518 andmemory partition unit. In at least one embodiment, when configured forgeneral purpose parallel computation, SM 3500 writes commands thatscheduler unit 3504 can use to launch new work on DPCs.

In at least one embodiment, a PPU is included in or coupled to a desktopcomputer, a laptop computer, a tablet computer, servers, supercomputers,a smart-phone (e.g., a wireless, hand-held device), personal digitalassistant (“PDA”), a digital camera, a vehicle, a head mounted display,a hand-held electronic device, and more. In at least one embodiment, aPPU is embodied on a single semiconductor substrate. In at least oneembodiment, a PPU is included in a system-on-a-chip (“SoC”) along withone or more other devices such as additional PPUs, memory, a reducedinstruction set computer (“RISC”) CPU, a memory management unit (“MMU”),a digital-to-analog converter (“DAC”), and like.

In at least one embodiment, a PPU may be included on a graphics cardthat includes one or more memory devices. In at least one embodiment,that graphics card may be configured to interface with a PCIe slot on amotherboard of a desktop computer. In at least one embodiment, that PPUmay be an integrated graphics processing unit (“iGPU”) included inchipset of a motherboard.

Inference and/or training logic 115 are used to perform inferencingand/or training operations associated with one or more embodiments.Details regarding inference and/or training logic 115 are providedherein in conjunction with FIGS. 1A and/or 1B. In at least oneembodiment, deep learning application processor is used to train amachine learning model, such as a neural network, to predict or inferinformation provided to SM 3500. In at least one embodiment, SM 3500 isused to infer or predict information based on a trained machine learningmodel (e.g., neural network) that has been trained by another processoror system or by SM 3500. In at least one embodiment, SM 3500 may be usedto perform one or more neural network use cases described herein.

Embodiments are disclosed related a virtualized computing platform foradvanced computing.

With reference to FIG. 36, FIG. 36 is an example data flow diagram for aprocess 3600 of generating and deploying a processing and inferencingpipeline, in accordance with at least one embodiment. In at least oneembodiment, process 3600 may be deployed to perform game namerecognition analysis and inferencing on user feedback data at one ormore facilities 3602, such as a data center.

In at least one embodiment, process 3600 may be executed within atraining system 3604 and/or a deployment system 3606. In at least oneembodiment, training system 3604 may be used to perform training,deployment, and implementation of machine learning models (e.g., neuralnetworks, object detection algorithms, computer vision algorithms, etc.)for use in deployment system 3606. In at least one embodiment,deployment system 3606 may be configured to offload processing andcompute resources among a distributed computing environment to reduceinfrastructure requirements at facility 3602. In at least oneembodiment, deployment system 3606 may provide a streamlined platformfor selecting, customizing, and implementing virtual instruments for usewith computing devices at facility 3602. In at least one embodiment,virtual instruments may include software-defined applications forperforming one or more processing operations with respect to feedbackdata. In at least one embodiment, one or more applications in a pipelinemay use or call upon services (e.g., inference, visualization, compute,AI, etc.) of deployment system 3606 during execution of applications.

In at least one embodiment, some of applications used in advancedprocessing and inferencing pipelines may use machine learning models orother AI to perform one or more processing steps. In at least oneembodiment, machine learning models may be trained at facility 3602using feedback data 3608 (such as feedback data) stored at facility 3602or feedback data 3608 from another facility or facilities, or acombination thereof. In at least one embodiment, training system 3604may be used to provide applications, services, and/or other resourcesfor generating working, deployable machine learning models fordeployment system 3606.

In at least one embodiment, a model registry 3624 may be backed byobject storage that may support versioning and object metadata. In atleast one embodiment, object storage may be accessible through, forexample, a cloud storage (e.g., a cloud 3726 of FIG. 37) compatibleapplication programming interface (API) from within a cloud platform. Inat least one embodiment, machine learning models within model registry3624 may uploaded, listed, modified, or deleted by developers orpartners of a system interacting with an API. In at least oneembodiment, an API may provide access to methods that allow users withappropriate credentials to associate models with applications, such thatmodels may be executed as part of execution of containerizedinstantiations of applications.

In at least one embodiment, a training pipeline 3704 (FIG. 37) mayinclude a scenario where facility 3602 is training their own machinelearning model, or has an existing machine learning model that needs tobe optimized or updated. In at least one embodiment, feedback data 3608may be received from various channels, such as forums, web forms, orsimilar channels. In at least one embodiment, once feedback data 3608 isreceived, AI-assisted annotation 3610 may be used to aid in generatingannotations corresponding to feedback data 3608 to be used as groundtruth data for a machine learning model. In at least one embodiment,AI-assisted annotation 3610 may include one or more machine learningmodels (e.g., convolutional neural networks (CNNs)) that may be trainedto generate annotations corresponding to certain types of feedback data3608 (e.g., from certain devices) and/or certain types of anomalies infeedback data 3608. In at least one embodiment, AI-assisted annotations3610 may then be used directly, or may be adjusted or fine-tuned usingan annotation tool, to generate ground truth data. In at least oneembodiment, in some examples, labeled data 3612 may be used as groundtruth data for training a machine learning model. In at least oneembodiment, AI-assisted annotations 3610, labeled data 3612, or acombination thereof may be used as ground truth data for training amachine learning model. In at least one embodiment, a trained machinelearning model may be referred to as an output model 3616, and may beused by deployment system 3606, as described herein.

In at least one embodiment, training pipeline 3704 (FIG. 37) may includea scenario where facility 3602 needs a machine learning model for use inperforming one or more processing tasks for one or more applications indeployment system 3606, but facility 3602 may not currently have such amachine learning model (or may not have a model that is optimized,efficient, or effective for such purposes). In at least one embodiment,an existing machine learning model may be selected from model registry3624. In at least one embodiment, model registry 3624 may includemachine learning models trained to perform a variety of differentinference tasks on imaging data. In at least one embodiment, machinelearning models in model registry 3624 may have been trained on imagingdata from different facilities than facility 3602 (e.g., facilitiesremotely located). In at least one embodiment, machine learning modelsmay have been trained on imaging data from one location, two locations,or any number of locations. In at least one embodiment, when beingtrained on imaging data from a specific location, training may takeplace at that location, or at least in a manner that protectsconfidentiality of imaging data or restricts imaging data from beingtransferred off-premises (e.g., to comply with HIPAA regulations,privacy regulations, etc.). In at least one embodiment, once a model istrained—or partially trained—at one location, a machine learning modelmay be added to model registry 3624. In at least one embodiment, amachine learning model may then be retrained, or updated, at any numberof other facilities, and a retrained or updated model may be madeavailable in model registry 3624. In at least one embodiment, a machinelearning model may then be selected from model registry 3624—andreferred to as output model 3616—and may be used in deployment system3606 to perform one or more processing tasks for one or moreapplications of a deployment system.

In at least one embodiment, training pipeline 3704 (FIG. 37) may be usedin a scenario that includes facility 3602 requiring a machine learningmodel for use in performing one or more processing tasks for one or moreapplications in deployment system 3606, but facility 3602 may notcurrently have such a machine learning model (or may not have a modelthat is optimized, efficient, or effective for such purposes). In atleast one embodiment, a machine learning model selected from modelregistry 3624 might not be fine-tuned or optimized for feedback data3608 generated at facility 3602 because of differences in populations,genetic variations, robustness of training data used to train a machinelearning model, diversity in anomalies of training data, and/or otherissues with training data. In at least one embodiment, AI-assistedannotation 3610 may be used to aid in generating annotationscorresponding to feedback data 3608 to be used as ground truth data forretraining or updating a machine learning model. In at least oneembodiment, labeled data 3612 may be used as ground truth data fortraining a machine learning model. In at least one embodiment,retraining or updating a machine learning model may be referred to asmodel training 3614. In at least one embodiment, model training3614—e.g., AI-assisted annotations 3610, labeled data 3612, or acombination thereof—may be used as ground truth data for retraining orupdating a machine learning model.

In at least one embodiment, deployment system 3606 may include software3618, services 3620, hardware 3622, and/or other components, features,and functionality. In at least one embodiment, deployment system 3606may include a software “stack,” such that software 3618 may be built ontop of services 3620 and may use services 3620 to perform some or all ofprocessing tasks, and services 3620 and software 3618 may be built ontop of hardware 3622 and use hardware 3622 to execute processing,storage, and/or other compute tasks of deployment system 3606.

In at least one embodiment, software 3618 may include any number ofdifferent containers, where each container may execute an instantiationof an application. In at least one embodiment, each application mayperform one or more processing tasks in an advanced processing andinferencing pipeline (e.g., inferencing, object detection, featuredetection, segmentation, image enhancement, calibration, etc.). In atleast one embodiment, for each type of computing device there may be anynumber of containers that may perform a data processing task withrespect to feedback data 3608 (or other data types, such as thosedescribed herein). In at least one embodiment, an advanced processingand inferencing pipeline may be defined based on selections of differentcontainers that are desired or required for processing feedback data3608, in addition to containers that receive and configure imaging datafor use by each container and/or for use by facility 3602 afterprocessing through a pipeline (e.g., to convert outputs back to a usabledata type for storage and display at facility 3602). In at least oneembodiment, a combination of containers within software 3618 (e.g., thatmake up a pipeline) may be referred to as a virtual instrument (asdescribed in more detail herein), and a virtual instrument may leverageservices 3620 and hardware 3622 to execute some or all processing tasksof applications instantiated in containers.

In at least one embodiment, data may undergo pre-processing as part ofdata processing pipeline to prepare data for processing by one or moreapplications. In at least one embodiment, post-processing may beperformed on an output of one or more inferencing tasks or otherprocessing tasks of a pipeline to prepare an output data for a nextapplication and/or to prepare output data for transmission and/or use bya user (e.g., as a response to an inference request). In at least oneembodiment, inferencing tasks may be performed by one or more machinelearning models, such as trained or deployed neural networks, which mayinclude output models 3616 of training system 3604.

In at least one embodiment, tasks of data processing pipeline may beencapsulated in a container(s) that each represent a discrete, fullyfunctional instantiation of an application and virtualized computingenvironment that is able to reference machine learning models. In atleast one embodiment, containers or applications may be published into aprivate (e.g., limited access) area of a container registry (describedin more detail herein), and trained or deployed models may be stored inmodel registry 3624 and associated with one or more applications. In atleast one embodiment, images of applications (e.g., container images)may be available in a container registry, and once selected by a userfrom a container registry for deployment in a pipeline, an image may beused to generate a container for an instantiation of an application foruse by a user's system.

In at least one embodiment, developers may develop, publish, and storeapplications (e.g., as containers) for performing processing and/orinferencing on supplied data. In at least one embodiment, development,publishing, and/or storing may be performed using a software developmentkit (SDK) associated with a system (e.g., to ensure that an applicationand/or container developed is compliant with or compatible with asystem). In at least one embodiment, an application that is developedmay be tested locally (e.g., at a first facility, on data from a firstfacility) with an SDK which may support at least some of services 3620as a system (e.g., system 3700 of FIG. 37). In at least one embodiment,once validated by system 3700 (e.g., for accuracy, etc.), an applicationmay be available in a container registry for selection and/orimplementation by a user (e.g., a hospital, clinic, lab, healthcareprovider, etc.) to perform one or more processing tasks with respect todata at a facility (e.g., a second facility) of a user.

In at least one embodiment, developers may then share applications orcontainers through a network for access and use by users of a system(e.g., system 3700 of FIG. 37). In at least one embodiment, completedand validated applications or containers may be stored in a containerregistry and associated machine learning models may be stored in modelregistry 3624. In at least one embodiment, a requesting entity—whoprovides an inference or image processing request—may browse a containerregistry and/or model registry 3624 for an application, container,dataset, machine learning model, etc., select a desired combination ofelements for inclusion in data processing pipeline, and submit anprocessing request. In at least one embodiment, a request may includeinput data that is necessary to perform a request, and/or may include aselection of application(s) and/or machine learning models to beexecuted in processing a request. In at least one embodiment, a requestmay then be passed to one or more components of deployment system 3606(e.g., a cloud) to perform processing of data processing pipeline. In atleast one embodiment, processing by deployment system 3606 may includereferencing selected elements (e.g., applications, containers, models,etc.) from a container registry and/or model registry 3624. In at leastone embodiment, once results are generated by a pipeline, results may bereturned to a user for reference (e.g., for viewing in a viewingapplication suite executing on a local, on-premises workstation orterminal).

In at least one embodiment, to aid in processing or execution ofapplications or containers in pipelines, services 3620 may be leveraged.In at least one embodiment, services 3620 may include compute services,artificial intelligence (AI) services, visualization services, and/orother service types. In at least one embodiment, services 3620 mayprovide functionality that is common to one or more applications insoftware 3618, so functionality may be abstracted to a service that maybe called upon or leveraged by applications. In at least one embodiment,functionality provided by services 3620 may run dynamically and moreefficiently, while also scaling well by allowing applications to processdata in parallel (e.g., using a parallel computing platform 3730 (FIG.37)). In at least one embodiment, rather than each application thatshares a same functionality offered by a service 3620 being required tohave a respective instance of service 3620, service 3620 may be sharedbetween and among various applications. In at least one embodiment,services may include an inference server or engine that may be used forexecuting detection or segmentation tasks, as non-limiting examples. Inat least one embodiment, a model training service may be included thatmay provide machine learning model training and/or retrainingcapabilities . . . .

In at least one embodiment, where a service 3620 includes an AI service(e.g., an inference service), one or more machine learning modelsassociated with an application for anomaly detection (e.g., tumors,growth abnormalities, scarring, etc.) may be executed by calling upon(e.g., as an API call) an inference service (e.g., an inference server)to execute machine learning model(s), or processing thereof, as part ofapplication execution. In at least one embodiment, where anotherapplication includes one or more machine learning models forsegmentation tasks, an application may call upon an inference service toexecute machine learning models for performing one or more of processingoperations associated with segmentation tasks. In at least oneembodiment, software 3618 implementing advanced processing andinferencing pipeline may be streamlined because each application maycall upon a same inference service to perform one or more inferencingtasks.

In at least one embodiment, hardware 3622 may include GPUs, CPUs,graphics cards, an AI/deep learning system (e.g., an AI supercomputer,such as NVIDIA's DGX supercomputer system), a cloud platform, or acombination thereof. In at least one embodiment, different types ofhardware 3622 may be used to provide efficient, purpose-built supportfor software 3618 and services 3620 in deployment system 3606. In atleast one embodiment, use of GPU processing may be implemented forprocessing locally (e.g., at facility 3602), within an AI/deep learningsystem, in a cloud system, and/or in other processing components ofdeployment system 3606 to improve efficiency, accuracy, and efficacy ofgame name recognition.

In at least one embodiment, software 3618 and/or services 3620 may beoptimized for GPU processing with respect to deep learning, machinelearning, and/or high-performance computing, as non-limiting examples.In at least one embodiment, at least some of computing environment ofdeployment system 3606 and/or training system 3604 may be executed in adatacenter one or more supercomputers or high performance computingsystems, with GPU optimized software (e.g., hardware and softwarecombination of NVIDIA's DGX system). In at least one embodiment,hardware 3622 may include any number of GPUs that may be called upon toperform processing of data in parallel, as described herein. In at leastone embodiment, cloud platform may further include GPU processing forGPU-optimized execution of deep learning tasks, machine learning tasks,or other computing tasks. In at least one embodiment, cloud platform(e.g., NVIDIA's NGC) may be executed using an AI/deep learningsupercomputer(s) and/or GPU-optimized software (e.g., as provided onNVIDIA's DGX systems) as a hardware abstraction and scaling platform. Inat least one embodiment, cloud platform may integrate an applicationcontainer clustering system or orchestration system (e.g., KUBERNETES)on multiple GPUs to enable seamless scaling and load balancing.

FIG. 37 is a system diagram for an example system 3700 for generatingand deploying a deployment pipeline, in accordance with at least oneembodiment. In at least one embodiment, system 3700 may be used toimplement process 3600 of FIG. 36 and/or other processes includingadvanced processing and inferencing pipelines. In at least oneembodiment, system 3700 may include training system 3604 and deploymentsystem 3606. In at least one embodiment, training system 3604 anddeployment system 3606 may be implemented using software 3618, services3620, and/or hardware 3622, as described herein.

In at least one embodiment, system 3700 (e.g., training system 3604and/or deployment system 3006) may implemented in a cloud computingenvironment (e.g., using cloud 3726). In at least one embodiment, system3700 may be implemented locally with respect to a facility, or as acombination of both cloud and local computing resources. In at least oneembodiment, access to APIs in cloud 3726 may be restricted to authorizedusers through enacted security measures or protocols. In at least oneembodiment, a security protocol may include web tokens that may besigned by an authentication (e.g., AuthN, AuthZ, Gluecon, etc.) serviceand may carry appropriate authorization. In at least one embodiment,APIs of virtual instruments (described herein), or other instantiationsof system 3700, may be restricted to a set of public IPs that have beenvetted or authorized for interaction.

In at least one embodiment, various components of system 3700 maycommunicate between and among one another using any of a variety ofdifferent network types, including but not limited to local areanetworks (LANs) and/or wide area networks (WANs) via wired and/orwireless communication protocols. In at least one embodiment,communication between facilities and components of system 3700 (e.g.,for transmitting inference requests, for receiving results of inferencerequests, etc.) may be communicated over a data bus or data busses,wireless data protocols (Wi-Fi), wired data protocols (e.g., Ethernet),etc.

In at least one embodiment, training system 3604 may execute trainingpipelines 3704, similar to those described herein with respect to FIG.36. In at least one embodiment, where one or more machine learningmodels are to be used in deployment pipelines 3710 by deployment system3606, training pipelines 3704 may be used to train or retrain one ormore (e.g., pre-trained) models, and/or implement one or more ofpre-trained models 3706 (e.g., without a need for retraining orupdating). In at least one embodiment, as a result of training pipelines3704, output model(s) 3616 may be generated. In at least one embodiment,training pipelines 3704 may include any number of processing steps 37,AI-assisted annotation 3610, labeling or annotating of feedback data3608 to generate labeled data 3612, model selection from a modelregistry, model training 3614, training, retraining, or updating models,and/or other processing steps. In at least one embodiment, for differentmachine learning models used by deployment system 3606, differenttraining pipelines 3704 may be used. In at least one embodiment,training pipeline 3704 similar to a first example described with respectto FIG. 36 may be used for a first machine learning model, trainingpipeline 3704 similar to a second example described with respect to FIG.36 may be used for a second machine learning model, and trainingpipeline 3704 similar to a third example described with respect to FIG.36 may be used for a third machine learning model. In at least oneembodiment, any combination of tasks within training system 3604 may beused depending on what is required for each respective machine learningmodel. In at least one embodiment, one or more of machine learningmodels may already be trained and ready for deployment so machinelearning models may not undergo any processing by training system 3604,and may be implemented by deployment system 3606.

In at least one embodiment, output model(s) 3616 and/or pre-trainedmodel(s) 3706 may include any types of machine learning models dependingon implementation or embodiment. In at least one embodiment, and withoutlimitation, machine learning models used by system 3700 may includemachine learning model(s) using linear regression, logistic regression,decision trees, support vector machines (SVM), Naïve Bayes, k-nearestneighbor (Knn), K means clustering, random forest, dimensionalityreduction algorithms, gradient boosting algorithms, neural networks(e.g., auto-encoders, convolutional, recurrent, perceptrons, Long/ShortTerm Memory (LSTM), Bi-LSTM, Hopfield, Boltzmann, deep belief,deconvolutional, generative adversarial, liquid state machine, etc.),and/or other types of machine learning models.

In at least one embodiment, training pipelines 3704 may includeAI-assisted annotation. In at least one embodiment, labeled data 3612(e.g., traditional annotation) may be generated by any number oftechniques. In at least one embodiment, labels or other annotations maybe generated within a drawing program (e.g., an annotation program), acomputer aided design (CAD) program, a labeling program, another type ofprogram suitable for generating annotations or labels for ground truth,and/or may be hand drawn, in some examples. In at least one embodiment,ground truth data may be synthetically produced (e.g., generated fromcomputer models or renderings), real produced (e.g., designed andproduced from real-world data), machine-automated (e.g., using featureanalysis and learning to extract features from data and then generatelabels), human annotated (e.g., labeler, or annotation expert, defineslocation of labels), and/or a combination thereof. In at least oneembodiment, for each instance of feedback data 3608 (or other data typeused by machine learning models), there may be corresponding groundtruth data generated by training system 3604. In at least oneembodiment, AI-assisted annotation may be performed as part ofdeployment pipelines 3710; either in addition to, or in lieu ofAI-assisted annotation included in training pipelines 3704. In at leastone embodiment, system 3700 may include a multi-layer platform that mayinclude a software layer (e.g., software 3618) of diagnosticapplications (or other application types) that may perform one or moremedical imaging and diagnostic functions.

In at least one embodiment, a software layer may be implemented as asecure, encrypted, and/or authenticated API through which applicationsor containers may be invoked (e.g., called) from an externalenvironment(s) (e.g., facility 3602). In at least one embodiment,applications may then call or execute one or more services 3620 forperforming compute, AI, or visualization tasks associated withrespective applications, and software 3618 and/or services 3620 mayleverage hardware 3622 to perform processing tasks in an effective andefficient manner.

In at least one embodiment, deployment system 3606 may executedeployment pipelines 3710. In at least one embodiment, deploymentpipelines 3710 may include any number of applications that may besequentially, non-sequentially, or otherwise applied to feedback data(and/or other data types)—including AI-assisted annotation, as describedabove. In at least one embodiment, as described herein, a deploymentpipeline 3710 for an individual device may be referred to as a virtualinstrument for a device. In at least one embodiment, for a singledevice, there may be more than one deployment pipeline 3710 depending oninformation desired from data generated by a device.

In at least one embodiment, applications available for deploymentpipelines 3710 may include any application that may be used forperforming processing tasks on feedback data or other data from devices.In at least one embodiment, because various applications may sharecommon image operations, a data augmentation library (e.g., as one ofservices 3620) may be used to accelerate these operations. In at leastone embodiment, to avoid bottlenecks of conventional processingapproaches that rely on CPU processing, parallel computing platform 3730may be used for GPU acceleration of these processing tasks.

In at least one embodiment, deployment system 3606 may include a userinterface 3714 (e.g., a graphical user interface, a web interface, etc.)that may be used to select applications for inclusion in deploymentpipeline(s) 3710, arrange applications, modify or change applications orparameters or constructs thereof, use and interact with deploymentpipeline(s) 3710 during set-up and/or deployment, and/or to otherwiseinteract with deployment system 3606. In at least one embodiment,although not illustrated with respect to training system 3604, userinterface 3714 (or a different user interface) may be used for selectingmodels for use in deployment system 3606, for selecting models fortraining, or retraining, in training system 3604, and/or for otherwiseinteracting with training system 3604.

In at least one embodiment, pipeline manager 3712 may be used, inaddition to an application orchestration system 3728, to manageinteraction between applications or containers of deployment pipeline(s)3710 and services 3620 and/or hardware 3622. In at least one embodiment,pipeline manager 3712 may be configured to facilitate interactions fromapplication to application, from application to service 3620, and/orfrom application or service to hardware 3622. In at least oneembodiment, although illustrated as included in software 3618, this isnot intended to be limiting, and in some examples pipeline manager 3712may be included in services 3620. In at least one embodiment,application orchestration system 3728 (e.g., Kubernetes, DOCKER, etc.)may include a container orchestration system that may group applicationsinto containers as logical units for coordination, management, scaling,and deployment. In at least one embodiment, by associating applicationsfrom deployment pipeline(s) 3710 (e.g., a reconstruction application, asegmentation application, etc.) with individual containers, eachapplication may execute in a self-contained environment (e.g., at akernel level) to increase speed and efficiency.

In at least one embodiment, each application and/or container (or imagethereof) may be individually developed, modified, and deployed (e.g., afirst user or developer may develop, modify, and deploy a firstapplication and a second user or developer may develop, modify, anddeploy a second application separate from a first user or developer),which may allow for focus on, and attention to, a task of a singleapplication and/or container(s) without being hindered by tasks ofanother application(s) or container(s). In at least one embodiment,communication, and cooperation between different containers orapplications may be aided by pipeline manager 3712 and applicationorchestration system 3728. In at least one embodiment, so long as anexpected input and/or output of each container or application is knownby a system (e.g., based on constructs of applications or containers),application orchestration system 3728 and/or pipeline manager 3712 mayfacilitate communication among and between, and sharing of resourcesamong and between, each of applications or containers. In at least oneembodiment, because one or more of applications or containers indeployment pipeline(s) 3710 may share same services and resources,application orchestration system 3728 may orchestrate, load balance, anddetermine sharing of services or resources between and among variousapplications or containers. In at least one embodiment, a scheduler maybe used to track resource requirements of applications or containers,current usage or planned usage of these resources, and resourceavailability. In at least one embodiment, a scheduler may thus allocateresources to different applications and distribute resources between andamong applications in view of requirements and availability of a system.In some examples, a scheduler (and/or other component of applicationorchestration system 3728) may determine resource availability anddistribution based on constraints imposed on a system (e.g., userconstraints), such as quality of service (QoS), urgency of need for dataoutputs (e.g., to determine whether to execute real-time processing ordelayed processing), etc.

In at least one embodiment, services 3620 leveraged by and shared byapplications or containers in deployment system 3606 may include computeservices 3716, AI services 3718, visualization services 3720, and/orother service types. In at least one embodiment, applications may call(e.g., execute) one or more of services 3620 to perform processingoperations for an application. In at least one embodiment, computeservices 3716 may be leveraged by applications to performsuper-computing or other high-performance computing (HPC) tasks. In atleast one embodiment, compute service(s) 3716 may be leveraged toperform parallel processing (e.g., using a parallel computing platform3730) for processing data through one or more of applications and/or oneor more tasks of a single application, substantially simultaneously. Inat least one embodiment, parallel computing platform 3730 (e.g.,NVIDIA's CUDA) may enable general purpose computing on GPUs (GPGPU)(e.g., GPUs 3722). In at least one embodiment, a software layer ofparallel computing platform 3730 may provide access to virtualinstruction sets and parallel computational elements of GPUs, forexecution of compute kernels. In at least one embodiment, parallelcomputing platform 3730 may include memory and, in at least oneembodiment, a memory may be shared between and among multiplecontainers, and/or between and among different processing tasks within asingle container. In at least one embodiment, inter-processcommunication (IPC) calls may be generated for multiple containersand/or for multiple processes within a container to use same data from ashared segment of memory of parallel computing platform 3730 (e.g.,where multiple different stages of an application or multipleapplications are processing same information). In at least oneembodiment, rather than making a copy of data and moving data todifferent locations in memory (e.g., a read/write operation), same datain same location of a memory may be used for any number of processingtasks (e.g., at a same time, at different times, etc.). In at least oneembodiment, as data is used to generate new data as a result ofprocessing, this information of a new location of data may be stored andshared between various applications. In at least one embodiment,location of data and a location of updated or modified data may be partof a definition of how a payload is understood within containers.

In at least one embodiment, AI services 3718 may be leveraged to performinferencing services for executing machine learning model(s) associatedwith applications (e.g., tasked with performing one or more processingtasks of an application). In at least one embodiment, AI services 3718may leverage AI system 3724 to execute machine learning model(s) (e.g.,neural networks, such as CNNs) for segmentation, reconstruction, objectdetection, feature detection, classification, and/or other inferencingtasks. In at least one embodiment, applications of deploymentpipeline(s) 3710 may use one or more of output models 3616 from trainingsystem 3604 and/or other models of applications to perform inference onimaging data (e.g., DICOM data, RIS data, CIS data, REST compliant data,RPC data, raw data, etc.). In at least one embodiment, two or moreexamples of inferencing using application orchestration system 3728(e.g., a scheduler) may be available. In at least one embodiment, afirst category may include a high priority/low latency path that mayachieve higher service level agreements, such as for performinginference on urgent requests during an emergency, or for a radiologistduring diagnosis. In at least one embodiment, a second category mayinclude a standard priority path that may be used for requests that maybe non-urgent or where analysis may be performed at a later time. In atleast one embodiment, application orchestration system 3728 maydistribute resources (e.g., services 3620 and/or hardware 3622) based onpriority paths for different inferencing tasks of AI services 3718.

In at least one embodiment, shared storage may be mounted to AI services3718 within system 3700. In at least one embodiment, shared storage mayoperate as a cache (or other storage device type) and may be used toprocess inference requests from applications. In at least oneembodiment, when an inference request is submitted, a request may bereceived by a set of API instances of deployment system 3606, and one ormore instances may be selected (e.g., for best fit, for load balancing,etc.) to process a request. In at least one embodiment, to process arequest, a request may be entered into a database, a machine learningmodel may be located from model registry 3624 if not already in a cache,a validation step may ensure appropriate machine learning model isloaded into a cache (e.g., shared storage), and/or a copy of a model maybe saved to a cache. In at least one embodiment, a scheduler (e.g., ofpipeline manager 3712) may be used to launch an application that isreferenced in a request if an application is not already running or ifthere are not enough instances of an application. In at least oneembodiment, if an inference server is not already launched to execute amodel, an inference server may be launched. In at least one embodiment,any number of inference servers may be launched per model. In at leastone embodiment, in a pull model, in which inference servers areclustered, models may be cached whenever load balancing is advantageous.In at least one embodiment, inference servers may be statically loadedin corresponding, distributed servers.

In at least one embodiment, inferencing may be performed using aninference server that runs in a container. In at least one embodiment,an instance of an inference server may be associated with a model (andoptionally a plurality of versions of a model). In at least oneembodiment, if an instance of an inference server does not exist when arequest to perform inference on a model is received, a new instance maybe loaded. In at least one embodiment, when starting an inferenceserver, a model may be passed to an inference server such that a samecontainer may be used to serve different models so long as inferenceserver is running as a different instance.

In at least one embodiment, during application execution, an inferencerequest for a given application may be received, and a container (e.g.,hosting an instance of an inference server) may be loaded (if notalready), and a start procedure may be called. In at least oneembodiment, pre-processing logic in a container may load, decode, and/orperform any additional pre-processing on incoming data (e.g., using aCPU(s) and/or GPU(s)). In at least one embodiment, once data is preparedfor inference, a container may perform inference as necessary on data.In at least one embodiment, this may include a single inference call onone image (e.g., a hand X-ray), or may require inference on hundreds ofimages (e.g., a chest CT). In at least one embodiment, an applicationmay summarize results before completing, which may include, withoutlimitation, a single confidence score, pixel level-segmentation,voxel-level segmentation, generating a visualization, or generating textto summarize findings. In at least one embodiment, different models orapplications may be assigned different priorities. For example, somemodels may have a real-time (TAT less than one minute) priority whileothers may have lower priority (e.g., TAT less than 10 minutes). In atleast one embodiment, model execution times may be measured fromrequesting institution or entity and may include partner networktraversal time, as well as execution on an inference service.

In at least one embodiment, transfer of requests between services 3620and inference applications may be hidden behind a software developmentkit (SDK), and robust transport may be provide through a queue. In atleast one embodiment, a request will be placed in a queue via an API foran individual application/tenant ID combination and an SDK will pull arequest from a queue and give a request to an application. In at leastone embodiment, a name of a queue may be provided in an environment fromwhere an SDK will pick it up. In at least one embodiment, asynchronouscommunication through a queue may be useful as it may allow any instanceof an application to pick up work as it becomes available. In at leastone embodiment, results may be transferred back through a queue, toensure no data is lost. In at least one embodiment, queues may alsoprovide an ability to segment work, as highest priority work may go to aqueue with most instances of an application connected to it, whilelowest priority work may go to a queue with a single instance connectedto it that processes tasks in an order received. In at least oneembodiment, an application may run on a GPU-accelerated instancegenerated in cloud 3726, and an inference service may performinferencing on a GPU.

In at least one embodiment, visualization services 3720 may be leveragedto generate visualizations for viewing outputs of applications and/ordeployment pipeline(s) 3710. In at least one embodiment, GPUs 3722 maybe leveraged by visualization services 3720 to generate visualizations.In at least one embodiment, rendering effects, such as ray-tracing, maybe implemented by visualization services 3720 to generate higher qualityvisualizations. In at least one embodiment, visualizations may include,without limitation, 2D image renderings, 3D volume renderings, 3D volumereconstruction, 2D tomographic slices, virtual reality displays,augmented reality displays, etc. In at least one embodiment, virtualizedenvironments may be used to generate a virtual interactive display orenvironment (e.g., a virtual environment) for interaction by users of asystem (e.g., doctors, nurses, radiologists, etc.). In at least oneembodiment, visualization services 3720 may include an internalvisualizer, cinematics, and/or other rendering or image processingcapabilities or functionality (e.g., ray tracing, rasterization,internal optics, etc.).

In at least one embodiment, hardware 3622 may include GPUs 3722, AIsystem 3724, cloud 3726, and/or any other hardware used for executingtraining system 3604 and/or deployment system 3606. In at least oneembodiment, GPUs 3722 (e.g., NVIDIA's TESLA and/or QUADRO GPUs) mayinclude any number of GPUs that may be used for executing processingtasks of compute services 3716, AI services 3718, visualization services3720, other services, and/or any of features or functionality ofsoftware 3618. For example, with respect to AI services 3718, GPUs 3722may be used to perform pre-processing on imaging data (or other datatypes used by machine learning models), post-processing on outputs ofmachine learning models, and/or to perform inferencing (e.g., to executemachine learning models). In at least one embodiment, cloud 3726, AIsystem 3724, and/or other components of system 3700 may use GPUs 3722.In at least one embodiment, cloud 3726 may include a GPU-optimizedplatform for deep learning tasks. In at least one embodiment, AI system3724 may use GPUs, and cloud 3726—or at least a portion tasked with deeplearning or inferencing—may be executed using one or more AI systems3724. As such, although hardware 3622 is illustrated as discretecomponents, this is not intended to be limiting, and any components ofhardware 3622 may be combined with, or leveraged by, any othercomponents of hardware 3622.

In at least one embodiment, AI system 3724 may include a purpose-builtcomputing system (e.g., a super-computer or an HPC) configured forinferencing, deep learning, machine learning, and/or other artificialintelligence tasks. In at least one embodiment, AI system 3724 (e.g.,NVIDIA's DGX) may include GPU-optimized software (e.g., a softwarestack) that may be executed using a plurality of GPUs 3722, in additionto CPUs, RAM, storage, and/or other components, features, orfunctionality. In at least one embodiment, one or more AI systems 3724may be implemented in cloud 3726 (e.g., in a data center) for performingsome or all of AI-based processing tasks of system 3700.

In at least one embodiment, cloud 3726 may include a GPU-acceleratedinfrastructure (e.g., NVIDIA's NGC) that may provide a GPU-optimizedplatform for executing processing tasks of system 3700. In at least oneembodiment, cloud 3726 may include an AI system(s) 3724 for performingone or more of AI-based tasks of system 3700 (e.g., as a hardwareabstraction and scaling platform). In at least one embodiment, cloud3726 may integrate with application orchestration system 3728 leveragingmultiple GPUs to enable seamless scaling and load balancing between andamong applications and services 3620. In at least one embodiment, cloud3726 may tasked with executing at least some of services 3620 of system3700, including compute services 3716, AI services 3718, and/orvisualization services 3720, as described herein. In at least oneembodiment, cloud 3726 may perform small and large batch inference(e.g., executing NVIDIA's TENSOR RT), provide an accelerated parallelcomputing API and platform 3730 (e.g., NVIDIA's CUDA), executeapplication orchestration system 3728 (e.g., KUBERNETES), provide agraphics rendering API and platform (e.g., for ray-tracing, 2D graphics,3D graphics, and/or other rendering techniques to produce higher qualitycinematics), and/or may provide other functionality for system 3700.

In at least one embodiment, in an effort to preserve patientconfidentiality (e.g., where patient data or records are to be usedoff-premises), cloud 3726 may include a registry—such as a deep learningcontainer registry. In at least one embodiment, a registry may storecontainers for instantiations of applications that may performpre-processing, post-processing, or other processing tasks on patientdata. In at least one embodiment, cloud 3726 may receive data thatincludes patient data as well as sensor data in containers, performrequested processing for just sensor data in those containers, and thenforward a resultant output and/or visualizations to appropriate partiesand/or devices (e.g., on-premises medical devices used for visualizationor diagnoses), all without having to extract, store, or otherwise accesspatient data. In at least one embodiment, confidentiality of patientdata is preserved in compliance with HIPAA and/or other dataregulations.

In clause 1, a processor comprising: two or more parallel circuits toperform two or more portions of a non-maximum suppression (NMS)algorithm in parallel to remove one or more redundant bounding boxescorresponding to one or more objects within one or more digital images.

In clause 2, a processor of clause 1, wherein two or more parallelcircuits, to perform two or more portions of NMS algorithm in parallel,are to: initiate a plurality of suppression processes to remove one ormore redundant bounding boxes corresponding to one or more objects; anddefine an area that covers a subset of a plurality of bounding boxes foreach suppression process.

In clause 3, a processor of any of clauses 1-2, wherein two or moreparallel circuits, to perform two or more portions of NMS algorithm inparallel, are to: identify a set of candidate points from an outputfeature map comprising a plurality of points, each point in outputfeature map corresponding to a bounding box and comprising a confidencescore, wherein each point of set of candidate points comprises aconfidence score that satisfies a confidence threshold; and cause eachof a plurality of parallel suppression processes to be performed inconnection with a respective candidate point, wherein each of pluralityof parallel suppression processes is to identify a set of neighboringpoints that are within an area associated with respective candidatepoint.

In clause 4, a processor of any of clauses 1-3, wherein each ofplurality of parallel suppression processes is to: calculate anintersection over union (IoU) value of respective candidate point and aneighboring point in identified set; determine whether IoU valuesatisfies an IoU threshold and a confidence score of candidate pointsatisfies a criterion pertaining to a confidence score of neighboringpoint; and identify candidate point as a redundant bounding box to beremoved responsive to IoU value satisfying IoU threshold and confidencescore satisfying criterion pertaining to confidence score of neighboringpoint.

In clause 5, a processor of any of clauses 1-4, wherein, to identify setof neighboring points, parallel suppression process is to: calculate adistance between respective candidate point and a second point in outputfeature map; and identify second point as a neighboring point responsiveto distance satisfying a distance threshold, wherein distance thresholdcorresponds to area associated with respective candidate point.

In clause 6, a processor of any of clauses 1-5, wherein, to calculatedistance, parallel suppression process is to calculate a cosine distancebetween respective candidate point and second point.

In clause 7, a processor of any of clauses 1-6, wherein two or moreparallel circuits are to use a neural network to detect one or moreobjects within one or more digital images, and wherein NMS algorithm isperformed as a layer of neural network.

In clause 8, a processor of any of clauses 1-7, wherein two or moreparallel circuits, to perform two or more portions of NMS algorithm inparallel, are to: identify a set of candidate boxes comprising a set ofcandidate points from an output feature map comprising a plurality ofpoints, each point in output feature map corresponding to a first anchorbox with a first confidence score and a second anchor box with a secondconfidence score, wherein at least one of first confidence scoresatisfies a first confidence threshold or second confidence scoresatisfies a second confidence threshold; and initiate each of aplurality of parallel suppression processes in connection with arespective candidate point, wherein each of plurality of parallelsuppression processes is to identify at least one of a first set ofneighboring points that are within a first area associated withrespective candidate point or a second set of neighboring points thatare within a second area associated with respective candidate point.

In clause 9, a system comprises: two or more circuits to perform two ormore portions of a non-maximum suppression (NMS) algorithm in parallelto remove one or more redundant bounding boxes corresponding to one ormore objects within one or more digital images; and one or more memoriesto store parameters associated with NMS algorithm.

In clause 10, a system of clause 9, wherein two or more circuits, toperform two or more portions of NMS algorithm in parallel, is to:initiate a plurality of parallel suppression processes to remove one ormore redundant bounding boxes corresponding to one or more objects; anddefine an area that covers a subset of a plurality of bounding boxes foreach suppression process.

In clause 11, a system of any of clauses 9-10, wherein two or morecircuits are to use one or more neural networks to detect one or moreobjects within one or more digital images, wherein neural networkcomprise a layer to perform NMS algorithm in parallel.

In clause 12, a system of any of clauses 9-11, wherein two or morecircuits are to use one or more neural networks comprising: multiplelayers to output an output feature map comprising a plurality of points,each point in output feature map corresponding to a bounding box and acomprising a confidence score; and a layer to identify a set ofcandidate points from output feature map, wherein each point of set ofcandidate points comprises a confidence score that satisfies aconfidence threshold, wherein layer is to cause each of a plurality ofparallel suppression processes to be performed in connection with arespective candidate point, and wherein each of plurality of parallelsuppression processes is to identify a set of neighboring points thatare within an area associated with respective candidate point.

In clause 13, a system of any of clauses 9-12, wherein each of pluralityof parallel suppression processes is to: calculate an intersection overunion (IoU) value of respective candidate point and a neighboring pointin identified set; determine whether IoU value satisfies an IoUthreshold and a confidence score of candidate point satisfies acriterion pertaining to a confidence score of neighboring point; andidentify candidate point as a redundant bounding box to be removedresponsive to IoU value satisfying IoU threshold and confidence scoresatisfying criterion pertaining to confidence score of neighboringpoint.

In clause 14, a system of any of clauses 9-13, wherein, to identify setof neighboring points, parallel suppression process is to: calculate adistance between respective candidate point and a second point in outputfeature map; and identify second point as a neighboring point responsiveto distance satisfying a distance threshold, wherein distance thresholdcorresponds to area associated with respective candidate point.

In clause 15, a system of any of clauses 9-14, wherein, to calculatedistance, parallel suppression process is to calculate a cosine distancebetween respective candidate point and second point.

In clause 16, a system of any of clauses 9-15, wherein two or morecircuits, to perform two or more portions of NMS algorithm in parallel,is to: identify a set of candidate boxes comprising a set of candidatepoints from an output feature map comprising a plurality of points, eachpoint in output feature map corresponding to a first anchor box with afirst confidence score and a second anchor box with a second confidencescore, wherein at least first confidence score satisfies a firstconfidence threshold or second confidence score satisfies a secondconfidence threshold; and initiate each of a plurality of parallelsuppression processes in connection with a respective candidate point,and wherein each of plurality of parallel suppression processes is toidentify at least one of a first set of neighboring points that arewithin a first area associated respective candidate point or a secondset of neighboring points that are within a second area associatedrespective candidate point.

In clause 17, a method comprises: identifying a plurality of boundingboxes corresponding to one or more objects within one or more digitalimages; and performing two or more portions of a non-maximum suppression(NMS) algorithm in parallel to remove one or more redundant boundingboxes from plurality of bounding boxes.

In clause 18, a method of clause 17, wherein performing two or moreportions of NMS algorithm in parallel comprises: initiating a pluralityof parallel suppression processes to remove one or more redundantbounding boxes corresponding to one or more objects; and defining anarea that covers a subset of a plurality of bounding boxes for eachsuppression process.

In clause 19, a system of any of clauses 17-18, wherein performing twoor more portions of NMS algorithm in parallel comprises: identifying aset of candidate points from an output feature map comprising aplurality of points, each point in output feature map corresponding to abounding box and comprising a confidence score, wherein each point ofset of candidate points comprises a confidence score that satisfies aconfidence threshold; and causing each of a plurality of parallelsuppression processes to be performed in connection with a respectivecandidate point, wherein each of plurality of parallel suppressionprocesses is to identify a set of neighboring points that are within anarea associated respective candidate point.

In clause 20, a system of any of clauses 17-19, wherein performing twoor more portions of NMS algorithm in parallel, for each of plurality ofparallel suppression processes, comprises: calculating an intersectionover union (IoU) value of respective candidate point and a neighboringpoint in identified set; determining whether IoU value is satisfies anIoU threshold and a confidence score of candidate point satisfies acriterion pertaining to a confidence score of neighboring point; andidentifying candidate point as a redundant bounding box to be removedresponsive to IoU value satisfying than IoU threshold and confidencescore satisfying criterion pertaining to confidence score of neighboringpoint.

In clause 21, a system of any of clauses 17-20, wherein identifying setof candidate points comprises: calculating a distance between respectivecandidate point and a second point in output feature map; andidentifying second point as a neighboring point responsive to distancesatisfying a distance threshold, wherein distance threshold correspondsto area associated with respective candidate point.

In clause 22, a system of any of clauses 17-21, wherein calculatingdistance comprises calculating a cosine distance between respectivecandidate point and second point.

In clause 23, a system of any of clauses 17-22, further comprisingdetecting, using a neural network, one or more objects within one ormore digital images, wherein performing two or more portions of NMSalgorithm in parallel is performed in a layer of neural network.

In clause 24, a system of any of clauses 17-23, wherein performing twoor more portions of NMS algorithm in parallel comprises: identifying aset of candidate boxes comprising a set of candidate points from anoutput feature map comprising a plurality of points, each point inoutput feature map corresponding to a first anchor box with a firstconfidence score and a second anchor box with a second confidence score,wherein at least one of first confidence score satisfies a firstconfidence threshold or second confidence score satisfies a secondconfidence threshold; and initiating each of a plurality of parallelsuppression processes in connection with a respective candidate point,wherein each of plurality of parallel suppression processes is toidentify at least one of a first set of neighboring points that arewithin a first area associated with respective candidate point or asecond set of neighboring points that are within a second areaassociated with respective candidate point.

In clause 25, a machine-readable medium having stored thereon a set ofinstructions, which if performed by one or more circuits, cause one ormore circuits to identify a plurality of bounding boxes corresponding toone or more objects within one or more digital images; and perform twoor more portions of a non-maximum suppression (NMS) algorithm inparallel to remove one or more redundant bounding boxes from pluralityof bounding boxes.

In clause 25, a machine-readable medium of clause 25, further comprisinginstructions, which if performed by one or more circuits, cause one ormore circuits to perform a method of any of clause 17-24.

In at least one embodiment, a single semiconductor platform may refer toa sole unitary semiconductor-based integrated circuit or chip. In atleast one embodiment, multi-chip modules may be used with increasedconnectivity which simulate on-chip operation, and make substantialimprovements over utilizing a conventional central processing unit(“CPU”) and bus implementation. In at least one embodiment, variousmodules may also be situated separately or in various combinations ofsemiconductor platforms per desires of user.

In at least one embodiment, referring back to FIG. 13, computer programsin form of machine-readable executable code or computer control logicalgorithms are stored in main memory 1304 and/or secondary storage.Computer programs, if executed by one or more processors, enable system1300 to perform various functions in accordance with at least oneembodiment. In at least one embodiment, memory 1304, storage, and/or anyother storage are possible examples of computer-readable media. In atleast one embodiment, secondary storage may refer to any suitablestorage device or system such as a hard disk drive and/or a removablestorage drive, representing a floppy disk drive, a magnetic tape drive,a compact disk drive, digital versatile disk (“DVD”) drive, recordingdevice, universal serial bus (“USB”) flash memory, etc. In at least oneembodiment, architecture and/or functionality of various previousfigures are implemented in context of CPU 1302, parallel processingsystem 1312, an integrated circuit capable of at least a portion ofcapabilities of both CPU 1302, parallel processing system 1312, achipset (e.g., a group of integrated circuits designed to work and soldas a unit for performing related functions, etc.), and/or any suitablecombination of integrated circuit(s).

In at least one embodiment, architecture and/or functionality of variousprevious figures are implemented in context of a general computersystem, a circuit board system, a game console system dedicated forentertainment purposes, an application-specific system, and more. In atleast one embodiment, computer system 1300 may take form of a desktopcomputer, a laptop computer, a tablet computer, servers, supercomputers,a smart-phone (e.g., a wireless, hand-held device), personal digitalassistant (“PDA”), a digital camera, a vehicle, a head mounted display,a hand-held electronic device, a mobile phone device, a television,workstation, game consoles, embedded system, and/or any other type oflogic.

In at least one embodiment, parallel processing system 1312 includes,without limitation, a plurality of parallel processing units (“PPUs”)1314 and associated memories 1316. In at least one embodiment, PPUs 1314are connected to a host processor or other peripheral devices via aninterconnect 1318 and a switch 1320 or multiplexer. In at least oneembodiment, parallel processing system 712 distributes computationaltasks across PPUs 1314 which can be parallelizable—for example, as partof distribution of computational tasks across multiple graphicsprocessing unit (“GPU”) thread blocks. In at least one embodiment,memory is shared and accessible (e.g., for read and/or write access)across some or all of PPUs 1314, although such shared memory may incurperformance penalties relative to use of local memory and registersresident to a PPU 1314. In at least one embodiment, operation of PPUs1314 is synchronized through use of a command such as _syncthreads( ),wherein all threads in a block (e.g., executed across multiple PPUs1314) to reach a certain point of execution of code before proceeding.

Other variations are within spirit of present disclosure. Thus, whiledisclosed techniques are susceptible to various modifications andalternative constructions, certain illustrated embodiments thereof areshown in drawings and have been described above in detail. It should beunderstood, however, that there is no intention to limit disclosure tospecific form or forms disclosed, but on contrary, intention is to coverall modifications, alternative constructions, and equivalents fallingwithin spirit and scope of disclosure, as defined in appended claims.

Use of terms “a” and “an” and “the” and similar referents in context ofdescribing disclosed embodiments (especially in context of followingclaims) are to be construed to cover both singular and plural, unlessotherwise indicated herein or clearly contradicted by context, and notas a definition of a term. Terms “comprising,” “having,” “including,”and “containing” are to be construed as open-ended terms (meaning“including, but not limited to,”) unless otherwise noted. “Connected,”when unmodified and referring to physical connections, is to beconstrued as partly or wholly contained within, attached to, or joinedtogether, even if there is something intervening. Recitation of rangesof values herein are merely intended to serve as a shorthand method ofreferring individually to each separate value falling within range,unless otherwise indicated herein and each separate value isincorporated into specification as if it were individually recitedherein. In at least one embodiment, use of term “set” (e.g., “a set ofitems”) or “subset” unless otherwise noted or contradicted by context,is to be construed as a nonempty collection comprising one or moremembers. Further, unless otherwise noted or contradicted by context,term “subset” of a corresponding set does not necessarily denote aproper subset of corresponding set, but subset and corresponding set maybe equal.

Conjunctive language, such as phrases of form “at least one of A, B, andC,” or “at least one of A, B and C,” unless specifically statedotherwise or otherwise clearly contradicted by context, is otherwiseunderstood with context as used in general to present that an item,term, etc., may be either A or B or C, or any nonempty subset of set ofA and B and C. For instance, in illustrative example of a set havingthree members, conjunctive phrases “at least one of A, B, and C” and “atleast one of A, B and C” refer to any of following sets: {A}, {B}, {C},{A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive language isnot generally intended to imply that certain embodiments require atleast one of A, at least one of B and at least one of C each to bepresent. In addition, unless otherwise noted or contradicted by context,term “plurality” indicates a state of being plural (e.g., “a pluralityof items” indicates multiple items). In at least one embodiment, numberof items in a plurality is at least two, but can be more when soindicated either explicitly or by context. Further, unless statedotherwise or otherwise clear from context, phrase “based on” means“based at least in part on” and not “based solely on.”

Operations of processes described herein can be performed in anysuitable order unless otherwise indicated herein or otherwise clearlycontradicted by context. In at least one embodiment, a process such asthose processes described herein (or variations and/or combinationsthereof) is performed under control of one or more computer systemsconfigured with executable instructions and is implemented as code(e.g., executable instructions, one or more computer programs or one ormore applications) executing collectively on one or more processors, byhardware or combinations thereof. In at least one embodiment, code isstored on a computer-readable storage medium, for example, in form of acomputer program comprising a plurality of instructions executable byone or more processors. In at least one embodiment, a computer-readablestorage medium is a non-transitory computer-readable storage medium thatexcludes transitory signals (e.g., a propagating transient electric orelectromagnetic transmission) but includes non-transitory data storagecircuitry (e.g., buffers, cache, and queues) within transceivers oftransitory signals. In at least one embodiment, code (e.g., executablecode or source code) is stored on a set of one or more non-transitorycomputer-readable storage media having stored thereon executableinstructions (or other memory to store executable instructions) that,when executed (i.e., as a result of being executed) by one or moreprocessors of a computer system, cause computer system to performoperations described herein. In at least one embodiment, set ofnon-transitory computer-readable storage media comprises multiplenon-transitory computer-readable storage media and one or more ofindividual non-transitory storage media of multiple non-transitorycomputer-readable storage media lack all of code while multiplenon-transitory computer-readable storage media collectively store all ofcode. In at least one embodiment, executable instructions are executedsuch that different instructions are executed by differentprocessors—for example, a non-transitory computer-readable storagemedium store instructions and a main central processing unit (“CPU”)executes some of instructions while a graphics processing unit (“GPU”)executes other instructions. In at least one embodiment, differentcomponents of a computer system have separate processors and differentprocessors execute different subsets of instructions.

Accordingly, in at least one embodiment, computer systems are configuredto implement one or more services that singly or collectively performoperations of processes described herein and such computer systems areconfigured with applicable hardware and/or software that enableperformance of operations. Further, a computer system that implements atleast one embodiment of present disclosure is a single device and, in atleast one other embodiment, is a distributed computer system comprisingmultiple devices that operate differently such that distributed computersystem performs operations described herein and such that a singledevice does not perform all operations.

Use of any and all examples, or exemplary language (e.g., “such as”)provided herein, is intended merely to better illuminate embodiments ofdisclosure and does not pose a limitation on scope of disclosure unlessotherwise claimed. No language in specification should be construed asindicating any non-claimed element as essential to practice ofdisclosure.

All references, including publications, patent applications, andpatents, cited herein are hereby incorporated by reference to sameextent as if each reference were individually and specifically indicatedto be incorporated by reference and were set forth in its entiretyherein.

In description and claims, terms “coupled” and “connected,” along withtheir derivatives, may be used. It should be understood that these termsmay be not intended as synonyms for each other. Rather, in particularexamples, “connected” or “coupled” may be used to indicate that two ormore elements are in direct or indirect physical or electrical contactwith each other. “Coupled” may also mean that two or more elements arenot in direct contact with each other, but yet still co-operate orinteract with each other.

Unless specifically stated otherwise, it may be appreciated thatthroughout specification terms such as “processing,” “computing,”“calculating,” “determining,” or like, refer to action and/or processesof a computer or computing system, or similar electronic computingdevice, that manipulate and/or transform data represented as physical,such as electronic, quantities within computing system's registersand/or memories into other data similarly represented as physicalquantities within computing system's memories, registers or other suchinformation storage, transmission or display devices.

In a similar manner, term “processor” may refer to any device or portionof a device that processes electronic data from registers and/or memoryand transform that electronic data into other electronic data that maybe stored in registers and/or memory. As non-limiting examples,“processor” may be a CPU or a GPU. A “computing platform” may compriseone or more processors. As used herein, “software” processes mayinclude, for example, software and/or hardware entities that performwork over time, such as tasks, threads, and intelligent agents. Also,each process may refer to multiple processes, for carrying outinstructions in sequence or in parallel, continuously or intermittently.In at least one embodiment, terms “system” and “method” are used hereininterchangeably insofar as system may embody one or more methods andmethods may be considered a system.

In present document, references may be made to obtaining, acquiring,receiving, or inputting analog or digital data into a subsystem,computer system, or computer-implemented machine. In at least oneembodiment, process of obtaining, acquiring, receiving, or inputtinganalog and digital data can be accomplished in a variety of ways such asby receiving data as a parameter of a function call or a call to anapplication programming interface. In at least one embodiment, processesof obtaining, acquiring, receiving, or inputting analog or digital datacan be accomplished by transferring data via a serial or parallelinterface. In at least one embodiment, processes of obtaining,acquiring, receiving, or inputting analog or digital data can beaccomplished by transferring data via a computer network from providingentity to acquiring entity. In at least one embodiment, references mayalso be made to providing, outputting, transmitting, sending, orpresenting analog or digital data. In various examples, processes ofproviding, outputting, transmitting, sending, or presenting analog ordigital data can be accomplished by transferring data as an input oroutput parameter of a function call, a parameter of an applicationprogramming interface or interprocess communication mechanism.

Although descriptions herein set forth example implementations ofdescribed techniques, other architectures may be used to implementdescribed functionality, and are intended to be within scope of thisdisclosure. Furthermore, although specific distributions ofresponsibilities may be defined above for purposes of description,various functions and responsibilities might be distributed and dividedin different ways, depending on circumstances.

Furthermore, although subject matter has been described in languagespecific to structural features and/or methodological acts, it is to beunderstood that subject matter claimed in appended claims is notnecessarily limited to specific features or acts described. Rather,specific features and acts are disclosed as exemplary forms ofimplementing claims.

What is claimed is:
 1. A processor comprising: two or more parallelcircuits to perform two or more portions of a non-maximum suppression(NMS) algorithm in parallel to remove one or more redundant boundingboxes corresponding to one or more objects within one or more digitalimages.
 2. The processor of claim 1, wherein the two or more parallelcircuits, to perform the two or more portions of the NMS algorithm inparallel, are to: initiate a plurality of suppression processes toremove the one or more redundant bounding boxes corresponding to the oneor more objects; and define an area that covers a subset of a pluralityof bounding boxes for each suppression process.
 3. The processor ofclaim 1, wherein the two or more parallel circuits, to perform the twoor more portions of the NMS algorithm in parallel, are to: identify aset of candidate points from an output feature map comprising aplurality of points, each point in the output feature map correspondingto a bounding box and comprising a confidence score, wherein each pointof the set of candidate points comprises a confidence score thatsatisfies a confidence threshold; and cause each of a plurality ofparallel suppression processes to be performed in connection with arespective candidate point, wherein each of the plurality of parallelsuppression processes is to identify a set of neighboring points thatare within an area associated with the respective candidate point. 4.The processor of claim 3, wherein each of the plurality of parallelsuppression processes is to: calculate an intersection over union (IoU)value of the respective candidate point and a neighboring point in theidentified set; determine whether the IoU value satisfies an IoUthreshold and a confidence score of the candidate point satisfies acriterion pertaining to a confidence score of the neighboring point; andidentify the candidate point as a redundant bounding box to be removedresponsive to the IoU value satisfying the IoU threshold and theconfidence score satisfying the criterion pertaining to the confidencescore of the neighboring point.
 5. The processor of claim 3, wherein, toidentify the set of neighboring points, the parallel suppression processis to: calculate a distance between the respective candidate point and asecond point in the output feature map; and identify the second point asa neighboring point responsive to the distance satisfying a distancethreshold, wherein the distance threshold corresponds to the areaassociated with the respective candidate point.
 6. The processor ofclaim 5, wherein, to calculate the distance, the parallel suppressionprocess is to calculate a cosine distance between the respectivecandidate point and the second point.
 7. The processor of claim 1,wherein the two or more parallel circuits are to use a neural network todetect the one or more objects within the one or more digital images,and wherein the NMS algorithm is performed as a layer of the neuralnetwork.
 8. The processor of claim 1, wherein the two or more parallelcircuits, to perform the two or more portions of the NMS algorithm inparallel, are to: identify a set of candidate boxes comprising a set ofcandidate points from an output feature map comprising a plurality ofpoints, each point in the output feature map corresponding to a firstanchor box with a first confidence score and a second anchor box with asecond confidence score, wherein at least one of the first confidencescore satisfies a first confidence threshold or the second confidencescore satisfies a second confidence threshold; and initiate each of aplurality of parallel suppression processes in connection with arespective candidate point, wherein each of the plurality of parallelsuppression processes is to identify at least one of a first set ofneighboring points that are within a first area associated with therespective candidate point or a second set of neighboring points thatare within a second area associated with the respective candidate point.9. A system comprising: two or more circuits to perform two or moreportions of a non-maximum suppression (NMS) algorithm in parallel toremove one or more redundant bounding boxes corresponding to one or moreobjects within one or more digital images; and one or more memories tostore parameters associated with the NMS algorithm.
 10. The system ofclaim 9, wherein the two or more circuits, to perform the two or moreportions of the NMS algorithm in parallel, is to: initiate a pluralityof parallel suppression processes to remove the one or more redundantbounding boxes corresponding to the one or more objects; and define anarea that covers a subset of a plurality of bounding boxes for eachsuppression process.
 11. The system of claim 9, wherein the two or morecircuits are to use one or more neural networks to detect the one ormore objects within the one or more digital images, wherein the neuralnetwork comprise a layer to perform the NMS algorithm in parallel. 12.The system of claim 9, wherein the two or more circuits are to use oneor more neural networks comprising: multiple layers to output an outputfeature map comprising a plurality of points, each point in the outputfeature map corresponding to a bounding box and a comprising aconfidence score; and a layer to identify a set of candidate points fromthe output feature map, wherein each point of the set of candidatepoints comprises a confidence score that satisfies a confidencethreshold, wherein the layer is to cause each of a plurality of parallelsuppression processes to be performed in connection with a respectivecandidate point, and wherein each of the plurality of parallelsuppression processes is to identify a set of neighboring points thatare within an area associated with the respective candidate point. 13.The system of claim 12, wherein each of the plurality of parallelsuppression processes is to: calculate an intersection over union (IoU)value of the respective candidate point and a neighboring point in theidentified set; determine whether the IoU value satisfies an IoUthreshold and a confidence score of the candidate point satisfies acriterion pertaining to a confidence score of the neighboring point; andidentify the candidate point as a redundant bounding box to be removedresponsive to the IoU value satisfying the IoU threshold and theconfidence score satisfying the criterion pertaining to the confidencescore of the neighboring point.
 14. The system of claim 12, wherein, toidentify the set of neighboring points, the parallel suppression processis to: calculate a distance between the respective candidate point and asecond point in the output feature map; and identify the second point asa neighboring point responsive to the distance satisfying a distancethreshold, wherein the distance threshold corresponds to the areaassociated with the respective candidate point.
 15. The system of claim14, wherein, to calculate the distance, the parallel suppression processis to calculate a cosine distance between the respective candidate pointand the second point.
 16. The system of claim 9, wherein the two or morecircuits, to perform the two or more portions of the NMS algorithm inparallel, is to: identify a set of candidate boxes comprising a set ofcandidate points from an output feature map comprising a plurality ofpoints, each point in the output feature map corresponding to a firstanchor box with a first confidence score and a second anchor box with asecond confidence score, wherein at least the first confidence scoresatisfies a first confidence threshold or the second confidence scoresatisfies a second confidence threshold; and initiate each of aplurality of parallel suppression processes in connection with arespective candidate point, and wherein each of the plurality ofparallel suppression processes is to identify at least one of a firstset of neighboring points that are within a first area associated therespective candidate point or a second set of neighboring points thatare within a second area associated the respective candidate point. 17.A method comprising: identifying a plurality of bounding boxescorresponding to one or more objects within one or more digital images;and performing two or more portions of a non-maximum suppression (NMS)algorithm in parallel to remove one or more redundant bounding boxesfrom the plurality of bounding boxes.
 18. The method of claim 17,wherein performing the two or more portions of the NMS algorithm inparallel comprises: initiating a plurality of parallel suppressionprocesses to remove the one or more redundant bounding boxescorresponding to the one or more objects; and defining an area thatcovers a subset of a plurality of bounding boxes for each suppressionprocess.
 19. The method of claim 17, wherein performing the two or moreportions of the NMS algorithm in parallel comprises: identifying a setof candidate points from an output feature map comprising a plurality ofpoints, each point in the output feature map corresponding to a boundingbox and comprising a confidence score, wherein each point of the set ofcandidate points comprises a confidence score that satisfies aconfidence threshold; and causing each of a plurality of parallelsuppression processes to be performed in connection with a respectivecandidate point, wherein each of the plurality of parallel suppressionprocesses is to identify a set of neighboring points that are within anarea associated the respective candidate point.
 20. The method of claim19, wherein performing the two or more portions of the NMS algorithm inparallel, for each of the plurality of parallel suppression processes,comprises: calculating an intersection over union (IoU) value of therespective candidate point and a neighboring point in the identifiedset; determining whether the IoU value is satisfies an IoU threshold anda confidence score of the candidate point satisfies a criterionpertaining to a confidence score of the neighboring point; andidentifying the candidate point as a redundant bounding box to beremoved responsive to the IoU value satisfying than the IoU thresholdand the confidence score satisfying the criterion pertaining to theconfidence score of the neighboring point.
 21. The method of claim 19,wherein identifying the set of candidate points comprises: calculating adistance between the respective candidate point and a second point inthe output feature map; and identifying the second point as aneighboring point responsive to the distance satisfying a distancethreshold, wherein the distance threshold corresponds to the areaassociated with the respective candidate point.
 22. The method of claim21, wherein calculating the distance comprises calculating a cosinedistance between the respective candidate point and the second point.23. The method of claim 17, further comprising detecting, using a neuralnetwork, the one or more objects within the one or more digital images,wherein performing the two or more portions of the NMS algorithm inparallel is performed in a layer of the neural network.
 24. The methodof claim 17, wherein performing the two or more portions of the NMSalgorithm in parallel comprises: identifying a set of candidate boxescomprising a set of candidate points from an output feature mapcomprising a plurality of points, each point in the output feature mapcorresponding to a first anchor box with a first confidence score and asecond anchor box with a second confidence score, wherein at least oneof the first confidence score satisfies a first confidence threshold orthe second confidence score satisfies a second confidence threshold; andinitiating each of a plurality of parallel suppression processes inconnection with a respective candidate point, wherein each of theplurality of parallel suppression processes is to identify at least oneof a first set of neighboring points that are within a first areaassociated with the respective candidate point or a second set ofneighboring points that are within a second area associated with therespective candidate point.